From: ichfly Date: Sun, 6 Dec 2015 18:16:37 +0000 (+0100) Subject: added src X-Git-Url: https://chaos.moe/g/?a=commitdiff_plain;h=eda490090d8f6c52727a0635957a32d2f4339339;p=console%2FXDS.git added src --- diff --git a/source/Bootloader.cpp b/source/Bootloader.cpp new file mode 100644 index 0000000..cbdb9c7 --- /dev/null +++ b/source/Bootloader.cpp @@ -0,0 +1,516 @@ +#include "Kernel.h" + +#include + +#include "Bootloader.h" + +//they are in mem in that order fs loader pm sm pix + + + +//tools +static u32 Read32revers(uint8_t p[4]) +{ + u32 temp = p[3] | p[2] << 8 | p[1] << 16 | p[0] << 24; + return temp; +} + +static u32 Read32(uint8_t p[4]) +{ + u32 temp = p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; + return temp; +} +static u64 Read64(uint8_t p[8]) +{ + u64 temp = p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24 | (u64)(p[4]) << 32 | (u64)(p[5]) << 40 | (u64)(p[6]) << 48 | (u64)(p[7]) << 56; + return temp; +} +static u16 Read16(uint8_t p[2]) +{ + u16 temp = p[0] | p[1] << 8; + return temp; +} +static u32 AlignPage(u32 in) +{ + return ((in + 0xFFF) / 0x1000) * 0x1000; +} +static u32 GetDecompressedSize(u8* compressed, u32 compressedsize) +{ + u8* footer = compressed + compressedsize - 8; + + u32 originalbottom = Read32(footer + 4); + return originalbottom + compressedsize; +} + +static int Decompress(u8* compressed, u32 compressedsize, u8* decompressed, u32 decompressedsize) +{ + + u8* footer = compressed + compressedsize - 8; + u32 buffertopandbottom = Read32(footer + 0); + u32 i, j; + u32 out = decompressedsize; + u32 index = compressedsize - ((buffertopandbottom >> 24) & 0xFF); + u32 segmentoffset; + u32 segmentsize; + u8 control; + u32 stopindex = compressedsize - (buffertopandbottom & 0xFFFFFF); + + memset(decompressed, 0, decompressedsize); + memcpy(decompressed, compressed, compressedsize); + + while (index > stopindex) { + control = compressed[--index]; + + for (i = 0; i<8; i++) { + if (index <= stopindex) + break; + if (index <= 0) + break; + if (out <= 0) + break; + + if (control & 0x80) { + if (index < 2) { + fprintf(stderr, "Error, compression out of bounds"); + goto clean; + } + + index -= 2; + + segmentoffset = compressed[index] | (compressed[index + 1] << 8); + segmentsize = ((segmentoffset >> 12) & 15) + 3; + segmentoffset &= 0x0FFF; + segmentoffset += 2; + + if (out < segmentsize) { + fprintf(stderr, "Error, compression out of bounds"); + goto clean; + } + + for (j = 0; j= decompressedsize) { + fprintf(stderr, "Error, compression out of bounds"); + goto clean; + } + + data = decompressed[out + segmentoffset]; + decompressed[--out] = data; + } + } + else { + if (out < 1) { + fprintf(stderr, "Error, compression out of bounds"); + goto clean; + } + decompressed[--out] = compressed[--index]; + } + control <<= 1; + } + } + + return 1; +clean: + return 0; +} + +KProcess* Boot_LoadFileFast(FILE* fd, u32 offset, u32* out_offset, KKernel * Kernel) +{ + + if (fseek(fd, offset, SEEK_SET) != 0) + { + XDSERROR("failed to seek."); + return NULL; + } + + exheader_header ex; + ctr_ncchheader loader_h; + u32 ncch_off = 0; + + // Read header. + if (fread(&loader_h, sizeof(loader_h), 1, fd) != 1) { + XDSERROR("failed to read header."); + return NULL; + } + + // Load NCCH + if (memcmp(&loader_h.magic, "NCCH", 4) != 0) { + XDSERROR("invalid magic.. wrong file?"); + return NULL; + } + + // Read Exheader. + if (fread(&ex, sizeof(ex), 1, fd) != 1) { + XDSERROR("failed to read exheader."); + return NULL; + } + + bool is_compressed = ex.codesetinfo.flags.flag & 1; + char namereal[9]; + strncpy(namereal, (char*)ex.codesetinfo.name, 9); + + // Read ExeFS. + u32 exefs_off = Read32(loader_h.exefsoffset) * 0x200; + u32 exefs_sz = Read32(loader_h.exefssize) * 0x200; + + if (fseek(fd, exefs_off + ncch_off + offset, SEEK_SET) != 0) + { + XDSERROR("failed to seek."); + return NULL; + } + + exefs_header eh; + if (fread(&eh, sizeof(eh), 1, fd) != 1) { + XDSERROR("failed to read ExeFS header."); + return NULL; + } + + for (u32 i = 0; i < 8; i++) { + u32 sec_size = Read32(eh.section[i].size); + u32 sec_off = Read32(eh.section[i].offset); + + if (sec_size == 0) + continue; + + eh.section[i].name[7] = '\0'; + + if (strcmp((char*)eh.section[i].name, ".code") == 0) { + sec_off += exefs_off + sizeof(eh); + if (fseek(fd, sec_off + ncch_off + offset, SEEK_SET) != 0) + { + XDSERROR("failed to seek."); + return NULL; + } + + u8* sec = (u8*)malloc(AlignPage(sec_size)); + if (sec == NULL) { + XDSERROR("section malloc failed."); + return NULL; + } + + if (fread(sec, sec_size, 1, fd) != 1) { + XDSERROR("section fread failed."); + free(sec); + return NULL; + } + + + // Decompress first section if flag set. + if (i == 0 && is_compressed) { + u32 dec_size = GetDecompressedSize(sec, sec_size); + u8* dec = (u8*)malloc(AlignPage(dec_size)); + + if (!dec) { + XDSERROR("decompressed data block allocation failed."); + free(sec); + return NULL; + } + + u32 firmexpected = Read32(ex.codesetinfo.text.codesize) + Read32(ex.codesetinfo.ro.codesize) + Read32(ex.codesetinfo.data.codesize); + + if (Decompress(sec, sec_size, dec, dec_size) == 0) { + XDSERROR("section decompression failed."); + free(sec); + free(dec); + return NULL; + } + + /*FILE * pFile; + pFile = fopen("code.code", "wb"); + if (pFile != NULL) + { + fwrite(dec, 1, dec_size, pFile); + fclose(pFile); + }*/ + + free(sec); + sec = dec; + sec_size = dec_size; + } + + // Load .code section. + u32 realcodesize = Read32(ex.codesetinfo.text.codesize); + u32 codesize = AlignPage(realcodesize); + u8* code = (u8*)malloc(codesize); + if (!code) { + XDSERROR("text data block allocation failed."); + free(sec); + return NULL; + } + memset(code,0, codesize); + memcpy(code, sec, realcodesize); + + u32 realrodatasize = Read32(ex.codesetinfo.ro.codesize); + u32 rodatasize = AlignPage(realrodatasize); + u8* rodata = (u8*)malloc(rodatasize); + if (!rodata) { + XDSERROR("rodata data block allocation failed."); + free(code); + free(sec); + return NULL; + } + memset(rodata, 0, rodatasize); + memcpy(rodata, sec + realcodesize, realrodatasize); + + u32 realdatasize = Read32(ex.codesetinfo.data.codesize); + u32 datasize = AlignPage(realdatasize); + u8* data = (u8*)malloc(datasize); + if (!data) { + XDSERROR("data data block allocation failed."); + free(code); + free(sec); + return NULL; + } + memset(data, 0, datasize); + memcpy(data, sec + realcodesize + realrodatasize, realdatasize); + + KCodeSet* Codeset = new KCodeSet( + code, codesize / 0x1000, + rodata, rodatasize/0x1000, + data, datasize / 0x1000, + AlignPage(Read32(ex.codesetinfo.bsssize)) / 0x1000, + Read64(loader_h.programid), + namereal + ); + + KProcess* process = new KProcess(Codeset, 28, (u32*)ex.arm11kernelcaps.descriptors, Kernel,true); + + //Start the process + + //map stack + u32 unused; + u32 stacksize = Read32(ex.codesetinfo.stacksize); + process->getMemoryMap()->ControlMemory(&unused, 0x10000000 - stacksize, 0, stacksize, OPERATION_COMMIT, PERMISSION_RW); + + KThread * thread = new KThread(SERVICECORE,process); + u32 startaddr = (process->m_exheader_flags & (1 << 12)) ? 0x14000000 : 0x00100000; + thread->m_context.reg_15 = startaddr; + thread->m_context.pc = startaddr; + thread->m_context.sp = 0x10000000; + thread->m_context.cpsr = 0x1F; + process->AddThread(thread); + + free(rodata); + free(data); + free(code); + free(sec); + + *out_offset = ftell(fd); + + //no need to register them with fs and sm the pm dose that on its own core stuff always dose that correctly + return process; + } + } + return NULL; +} +FILE* openapp(u32 titlehigh, u32 titlelow) //used by pm +{ + for (u32 i = 0; i < 0x1000; i++) //TODO search for the correct tmd that needs to be impr that is also only a hack normaly the data is loaded from .firm not from the FS + { + char string[0x100]; +#if EMU_PLATFORM == PLATFORM_WINDOWS + sprintf_s(string, 0x100, "./NAND/title/%08X/%08X/content/%08x.tmd", titlehigh, titlelow, i); +#else + snprintf(string, 0x100, "./NAND/title/%08X/%08X/content/%08x.tmd", titlehigh, titlelow, i); +#endif + FILE* fd = fopen(string, "rb"); + if (fd != NULL) + { + u8 temp[4]; + if (fread(temp, 4, 1, fd) != 1) + { + XDSERROR("reading tmd Signature Type"); + return NULL; + } + u32 Signature_Type = Read32revers(temp); + u32 y; + switch (Signature_Type) + { + case 0x010000: + y = 0x240; + break; + case 0x010001: + y = 0x140; + break; + case 0x010002: + y = 0x80; + break; + case 0x010003: + y = 0x240; + break; + case 0x010004: + y = 0x140; + break; + case 0x010005: + y = 0x80; + break; + default: + LOG("unknown Signature Type fallback"); + y = 0x140; + break; + } + if (fseek(fd, y + 0x9C4, SEEK_SET) != 0) + { + XDSERROR("reading tmd Signature Type"); + return NULL; + } + if (fread(temp, 4, 1, fd) != 1) + { + XDSERROR("reading tmd Signature Type"); + return NULL; + } + u32 index = Read32revers(temp); + fclose(fd); + +#if EMU_PLATFORM == PLATFORM_WINDOWS + sprintf_s(string, 0x100, "./NAND/title/%08x/%08x/content/%08x.app", titlehigh, titlelow, index); +#else + snprintf(string, 0x100, "./NAND/title/%08x/%08x/content/%08x.app", titlehigh, titlelow, index); +#endif + fd = fopen(string, "rb"); + if (fd == NULL) + { + XDSERROR("opening the container %s", string); + return NULL; + } + return fd; + } + } + return NULL; +} + +s64 FindRomFSOffset(FILE* fd, char* name, u64 &out_size, u8* hash_out) +{ + if (fd == NULL) + { + return -1; + } + fseek(fd, 0, SEEK_SET); + + + //open the container + exheader_header ex; + ctr_ncchheader loader_h; + u32 ncch_off = 0; + + // Read header. + if (fread(&loader_h, sizeof(loader_h), 1, fd) != 1) { + XDSERROR("failed to read header."); + return -1; + } + // Load NCCH + if (memcmp(&loader_h.magic, "NCCH", 4) != 0) { + XDSERROR("invalid magic.. wrong file?"); + return -1; + } + + // Read Exheader. + if (fread(&ex, sizeof(ex), 1, fd) != 1) { + XDSERROR("failed to read exheader."); + return -1; + } + + // Read ExeFS. + u32 exefs_off = Read32(loader_h.romfsoffset) * 0x200; + out_size = Read32(loader_h.romfssize) * 0x200; + + return exefs_off; +} + + +s64 FindTableOffset(FILE* fd,char* name,u64 &out_size, u8* hash_out) +{ + if (fd == NULL) + { + return -1; + } + fseek(fd, 0, SEEK_SET); + + + //open the container + exheader_header ex; + ctr_ncchheader loader_h; + u32 ncch_off = 0; + + // Read header. + if (fread(&loader_h, sizeof(loader_h), 1, fd) != 1) { + XDSERROR("failed to read header."); + return -1; + } + // Load NCCH + if (memcmp(&loader_h.magic, "NCCH", 4) != 0) { + XDSERROR("invalid magic.. wrong file?"); + return -1; + } + + // Read Exheader. + if (fread(&ex, sizeof(ex), 1, fd) != 1) { + XDSERROR("failed to read exheader."); + return -1; + } + + // Read ExeFS. + u32 exefs_off = Read32(loader_h.exefsoffset) * 0x200; + u32 exefs_sz = Read32(loader_h.exefssize) * 0x200; + + if (fseek(fd, exefs_off + ncch_off, SEEK_SET) != 0) + { + XDSERROR("failed to seek."); + return -2; + } + + exefs_header eh; + if (fread(&eh, sizeof(eh), 1, fd) != 1) { + XDSERROR("failed to read ExeFS header."); + return -1; + } + + for (u32 i = 0; i < 8; i++) { + u32 sec_size = Read32(eh.section[i].size); + u32 sec_off = Read32(eh.section[i].offset); + out_size = sec_size; + if (sec_size == 0) + continue; + + eh.section[i].name[7] = '\0'; + + if (hash_out != NULL) + { + memcpy(hash_out, eh.hashes[7-i], 0x20); + } + + //sec_off = 0; + + if (strcmp((char*)eh.section[i].name, name) == 0) { + return exefs_off + sizeof(eh) + sec_off; + } + } + XDSERROR("finding section"); + return -1; +} + +int Boot(KKernel* kernel) +{ + FILE* fd = openapp(0x00040138, 0x00000002);//this is firm + //open the firm to extrect the core modules + u64 temp; + s64 sec_off = FindTableOffset(fd, ".firm", temp, NULL); + u32 out_offset; + if (sec_off > 0) + { + KProcess* process = Boot_LoadFileFast(fd, sec_off + 0x200, &out_offset, kernel);//The first is most likely the NCCH container but that may change I don't know how to detect the correct container so I just do it by a static offset TODO + for (int j = 0; j < 4; j++) //boot all 5 + { + process = Boot_LoadFileFast(fd, (out_offset + 0x1FF)&~0x1FF, &out_offset, kernel); + } + fclose(fd); + return 0; //it worked + } + fclose(fd); + XDSERROR("finding .firm section"); + return -1; + XDSERROR("finding firm"); + return -1; + +} diff --git a/source/Main.cpp b/source/Main.cpp new file mode 100644 index 0000000..9e2d42b --- /dev/null +++ b/source/Main.cpp @@ -0,0 +1,51 @@ +#define NOMINMAX + +#include +#include "Kernel.h" +#include "Gui.h" +#include "Bootloader.h" + +#include "citraimport\GPU\window\emu_window_glfw.h" + +namespace VideoCore { + void Init(EmuWindow* emu_window); +} // namespace + + +static u8 code[0x1000000]; + +KKernel* mykernel; //this is a citra hack + +int main(int argc, char* argv[]) { + /*FILE* fd = fopen("code.bin", "rb"); + size_t size = fread(code, 1, sizeof(code), fd); + fclose(fd);*/ + + //citra hacks + + EmuWindow_GLFW window; + + VideoCore::Init(&window); + + //citra hacks end + + //MainWindow* wndMain = new MainWindow(); + mykernel = new KKernel(); + + Mem_Init(false); + Mem_SharedMemInit(); + + Boot(mykernel); + + //kernel->AddQuickCodeProcess(&code[0], size); + mykernel->ThreadsRunTemp(); + return 0; +} +extern "C" void citraFireInterrupt(int id) +{ + LOG("cirta fire %02x",id); + mykernel->FireInterrupt(id); +} +bool novideo = true; +extern "C" int citraPressedkey = 0; +extern "C" bool citraSettingSkipGSP = false; \ No newline at end of file diff --git a/source/arm/ArmCore.cpp b/source/arm/ArmCore.cpp new file mode 100644 index 0000000..1fa4bea --- /dev/null +++ b/source/arm/ArmCore.cpp @@ -0,0 +1,39 @@ +#include "Kernel.h" + +KArmCore::KArmCore(KKernel* kernel) : m_kernel(kernel), m_cpu() +{ + m_thread = NULL; +} +void KArmCore::SetThread(KThread* thread) +{ + if (m_thread) + { + m_cpu.SaveContext(m_thread->m_context); + } + + m_thread = thread; + + m_cpu.state->m_currentThread = m_thread; + m_cpu.LoadContext(m_thread->m_context); + m_cpu.state->m_MemoryMap = &m_thread->m_owner->m_memory; +} +u64 KArmCore::RunCycles(uint cycles) +{ + return m_cpu.Run(cycles); +} +void KArmCore::ReSchedule() +{ + m_cpu.PrepareReschedule(); +} +void KArmCore::SetRegister(uint id, uint data) +{ + m_cpu.SetReg(id, data); +} +void KArmCore::Addticks(int ticks) +{ + m_cpu.AddTicks(ticks); +} +s64 KArmCore::Getticks() +{ + return m_cpu.GetTicks(); +} \ No newline at end of file diff --git a/source/arm/arm_interface.h b/source/arm/arm_interface.h new file mode 100644 index 0000000..a617bda --- /dev/null +++ b/source/arm/arm_interface.h @@ -0,0 +1,118 @@ +// Copyright 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include "Common.h" + +/// Generic ARM11 CPU interface +class ARM_Interface { +public: + ARM_Interface() { + num_instructions = 0; + } + + virtual ~ARM_Interface() { + } + + /** + * Runs the CPU for the given number of instructions + * @param num_instructions Number of instructions to run + */ + u64 Run(int num_instructions) { + num_instructions = (int)ExecuteInstructions(num_instructions); + this->num_instructions += num_instructions; + return num_instructions; + } + + /// Step CPU by one instruction + void Step() { + Run(1); + } + + /** + * Set the Program Counter to an address + * @param addr Address to set PC to + */ + virtual void SetPC(u32 addr) = 0; + + /* + * Get the current Program Counter + * @return Returns current PC + */ + virtual u32 GetPC() const = 0; + + /** + * Get an ARM register + * @param index Register index (0-15) + * @return Returns the value in the register + */ + virtual u32 GetReg(int index) const = 0; + + /** + * Set an ARM register + * @param index Register index (0-15) + * @param value Value to set register to + */ + virtual void SetReg(int index, u32 value) = 0; + + /** + * Get the current CPSR register + * @return Returns the value of the CPSR register + */ + virtual u32 GetCPSR() const = 0; + + /** + * Set the current CPSR register + * @param cpsr Value to set CPSR to + */ + virtual void SetCPSR(u32 cpsr) = 0; + + /** + * Returns the number of clock ticks since the last rese + * @return Returns number of clock ticks + */ + virtual u64 GetTicks() const = 0; + + /** + * Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time) + * @param ticks Number of ticks to advance the CPU core + */ + virtual void AddTicks(u64 ticks) = 0; + + /** + * Saves the current CPU context + * @param ctx Thread context to save + */ + virtual void SaveContext(ThreadContext& ctx) = 0; + + /** + * Loads a CPU context + * @param ctx Thread context to load + */ + virtual void LoadContext(const ThreadContext& ctx) = 0; + + /// Prepare core for thread reschedule (if needed to correctly handle state) + virtual void PrepareReschedule() = 0; + + /// Getter for num_instructions + u64 GetNumInstructions() { + return num_instructions; + } + + s64 down_count; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop + +protected: + + /** + * Executes the given number of instructions + * @param num_instructions Number of instructions to executes + */ + virtual u64 ExecuteInstructions(int num_instructions) = 0; + +private: + + u64 num_instructions; ///< Number of instructions executed + +}; diff --git a/source/arm/disassembler/arm_disasm.cpp b/source/arm/disassembler/arm_disasm.cpp new file mode 100644 index 0000000..adaa08c --- /dev/null +++ b/source/arm/disassembler/arm_disasm.cpp @@ -0,0 +1,966 @@ +// Copyright 2006 The Android Open Source Project + +#include "Common.h" +#include "util/Common.h" + +#include "arm/disassembler/arm_disasm.h" + +static const char *cond_names[] = { + "eq", + "ne", + "cs", + "cc", + "mi", + "pl", + "vs", + "vc", + "hi", + "ls", + "ge", + "lt", + "gt", + "le", + "", + "RESERVED" +}; + +const char *opcode_names[] = { + "invalid", + "undefined", + "adc", + "add", + "and", + "b", + "bl", + "bic", + "bkpt", + "blx", + "bx", + "cdp", + "clz", + "cmn", + "cmp", + "eor", + "ldc", + "ldm", + "ldr", + "ldrb", + "ldrbt", + "ldrh", + "ldrsb", + "ldrsh", + "ldrt", + "mcr", + "mla", + "mov", + "mrc", + "mrs", + "msr", + "mul", + "mvn", + "orr", + "pld", + "rsb", + "rsc", + "sbc", + "smlal", + "smull", + "stc", + "stm", + "str", + "strb", + "strbt", + "strh", + "strt", + "sub", + "swi", + "swp", + "swpb", + "teq", + "tst", + "umlal", + "umull", + + "undefined", + "adc", + "add", + "and", + "asr", + "b", + "bic", + "bkpt", + "bl", + "blx", + "bx", + "cmn", + "cmp", + "eor", + "ldmia", + "ldr", + "ldrb", + "ldrh", + "ldrsb", + "ldrsh", + "lsl", + "lsr", + "mov", + "mul", + "mvn", + "neg", + "orr", + "pop", + "push", + "ror", + "sbc", + "stmia", + "str", + "strb", + "strh", + "sub", + "swi", + "tst", + + NULL +}; + +// Indexed by the shift type (bits 6-5) +static const char *shift_names[] = { + "LSL", + "LSR", + "ASR", + "ROR" +}; + +static const char* cond_to_str(int cond) { + return cond_names[cond]; +} + +std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn) +{ + Opcode opcode = Decode(insn); + switch (opcode) { + case OP_INVALID: + return "Invalid"; + case OP_UNDEFINED: + return "Undefined"; + case OP_ADC: + case OP_ADD: + case OP_AND: + case OP_BIC: + case OP_CMN: + case OP_CMP: + case OP_EOR: + case OP_MOV: + case OP_MVN: + case OP_ORR: + case OP_RSB: + case OP_RSC: + case OP_SBC: + case OP_SUB: + case OP_TEQ: + case OP_TST: + return DisassembleALU(opcode, insn); + case OP_B: + case OP_BL: + return DisassembleBranch(addr, opcode, insn); + case OP_BKPT: + return DisassembleBKPT(insn); + case OP_BLX: + // not supported yet + break; + case OP_BX: + return DisassembleBX(insn); + case OP_CDP: + return "cdp"; + case OP_CLZ: + return DisassembleCLZ(insn); + case OP_LDC: + return "ldc"; + case OP_LDM: + case OP_STM: + return DisassembleMemblock(opcode, insn); + case OP_LDR: + case OP_LDRB: + case OP_LDRBT: + case OP_LDRT: + case OP_STR: + case OP_STRB: + case OP_STRBT: + case OP_STRT: + return DisassembleMem(insn); + case OP_LDRH: + case OP_LDRSB: + case OP_LDRSH: + case OP_STRH: + return DisassembleMemHalf(insn); + case OP_MCR: + case OP_MRC: + return DisassembleMCR(opcode, insn); + case OP_MLA: + return DisassembleMLA(opcode, insn); + case OP_MRS: + return DisassembleMRS(insn); + case OP_MSR: + return DisassembleMSR(insn); + case OP_MUL: + return DisassembleMUL(opcode, insn); + case OP_PLD: + return DisassemblePLD(insn); + case OP_STC: + return "stc"; + case OP_SWI: + return DisassembleSWI(insn); + case OP_SWP: + case OP_SWPB: + return DisassembleSWP(opcode, insn); + case OP_UMLAL: + case OP_UMULL: + case OP_SMLAL: + case OP_SMULL: + return DisassembleUMLAL(opcode, insn); + default: + return "Error"; + } + return NULL; +} + +std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn) +{ + static const uint8_t kNoOperand1 = 1; + static const uint8_t kNoDest = 2; + static const uint8_t kNoSbit = 4; + + std::string rn_str; + std::string rd_str; + + uint8_t flags = 0; + uint8_t cond = (insn >> 28) & 0xf; + uint8_t is_immed = (insn >> 25) & 0x1; + uint8_t bit_s = (insn >> 20) & 1; + uint8_t rn = (insn >> 16) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint8_t immed = insn & 0xff; + + const char* opname = opcode_names[opcode]; + switch (opcode) { + case OP_CMN: + case OP_CMP: + case OP_TEQ: + case OP_TST: + flags = kNoDest | kNoSbit; + break; + case OP_MOV: + case OP_MVN: + flags = kNoOperand1; + break; + default: + break; + } + + // The "mov" instruction ignores the first operand (rn). + rn_str[0] = 0; + if ((flags & kNoOperand1) == 0) { + rn_str = Common::StringFromFormat("r%d, ", rn); + } + + // The following instructions do not write the result register (rd): + // tst, teq, cmp, cmn. + rd_str[0] = 0; + if ((flags & kNoDest) == 0) { + rd_str = Common::StringFromFormat("r%d, ", rd); + } + + const char *sbit_str = ""; + if (bit_s && !(flags & kNoSbit)) + sbit_str = "s"; + + if (is_immed) { + return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", + opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed); + } + + uint8_t shift_is_reg = (insn >> 4) & 1; + uint8_t rotate = (insn >> 8) & 0xf; + uint8_t rm = insn & 0xf; + uint8_t shift_type = (insn >> 5) & 0x3; + uint8_t rs = (insn >> 8) & 0xf; + uint8_t shift_amount = (insn >> 7) & 0x1f; + uint32_t rotated_val = immed; + uint8_t rotate2 = rotate << 1; + rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2)); + + if (!shift_is_reg && shift_type == 0 && shift_amount == 0) { + return Common::StringFromFormat("%s%s%s\t%s%sr%d", + opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); + } + + const char *shift_name = shift_names[shift_type]; + if (shift_is_reg) { + return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", + opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, + shift_name, rs); + } + if (shift_amount == 0) { + if (shift_type == 3) { + return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", + opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); + } + shift_amount = 32; + } + return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", + opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, + shift_name, shift_amount); +} + +std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint32_t offset = insn & 0xffffff; + // Sign-extend the 24-bit offset + if ((offset >> 23) & 1) + offset |= 0xff000000; + + // Pre-compute the left-shift and the prefetch offset + offset <<= 2; + offset += 8; + addr += offset; + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr); +} + +std::string ARM_Disasm::DisassembleBX(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rn = insn & 0xf; + return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn); +} + +std::string ARM_Disasm::DisassembleBKPT(uint32_t insn) +{ + uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf); + return Common::StringFromFormat("bkpt\t#%d", immed); +} + +std::string ARM_Disasm::DisassembleCLZ(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint8_t rm = insn & 0xf; + return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm); +} + +std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn) +{ + std::string tmp_reg; + std::string tmp_list; + + uint8_t cond = (insn >> 28) & 0xf; + uint8_t write_back = (insn >> 21) & 0x1; + uint8_t bit_s = (insn >> 22) & 0x1; + uint8_t is_up = (insn >> 23) & 0x1; + uint8_t is_pre = (insn >> 24) & 0x1; + uint8_t rn = (insn >> 16) & 0xf; + uint16_t reg_list = insn & 0xffff; + + const char *opname = opcode_names[opcode]; + + const char *bang = ""; + if (write_back) + bang = "!"; + + const char *carret = ""; + if (bit_s) + carret = "^"; + + const char *comma = ""; + tmp_list[0] = 0; + for (int ii = 0; ii < 16; ++ii) { + if (reg_list & (1 << ii)) { + tmp_list += Common::StringFromFormat("%sr%d", comma, ii); + comma = ","; + } + } + + const char *addr_mode = ""; + if (is_pre) { + if (is_up) { + addr_mode = "ib"; + } else { + addr_mode = "db"; + } + } else { + if (is_up) { + addr_mode = "ia"; + } else { + addr_mode = "da"; + } + } + + return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", + opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret); +} + +std::string ARM_Disasm::DisassembleMem(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t is_reg = (insn >> 25) & 0x1; + uint8_t is_load = (insn >> 20) & 0x1; + uint8_t write_back = (insn >> 21) & 0x1; + uint8_t is_byte = (insn >> 22) & 0x1; + uint8_t is_up = (insn >> 23) & 0x1; + uint8_t is_pre = (insn >> 24) & 0x1; + uint8_t rn = (insn >> 16) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint16_t offset = insn & 0xfff; + + const char *opname = "ldr"; + if (!is_load) + opname = "str"; + + const char *bang = ""; + if (write_back) + bang = "!"; + + const char *minus = ""; + if (is_up == 0) + minus = "-"; + + const char *byte = ""; + if (is_byte) + byte = "b"; + + if (is_reg == 0) { + if (is_pre) { + if (offset == 0) { + return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", + opname, cond_to_str(cond), byte, rd, rn); + } else { + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", + opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang); + } + } else { + const char *transfer = ""; + if (write_back) + transfer = "t"; + + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", + opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset); + } + } + + uint8_t rm = insn & 0xf; + uint8_t shift_type = (insn >> 5) & 0x3; + uint8_t shift_amount = (insn >> 7) & 0x1f; + + const char *shift_name = shift_names[shift_type]; + + if (is_pre) { + if (shift_amount == 0) { + if (shift_type == 0) { + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", + opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); + } + if (shift_type == 3) { + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", + opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); + } + shift_amount = 32; + } + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", + opname, cond_to_str(cond), byte, rd, rn, minus, rm, + shift_name, shift_amount, bang); + } + + const char *transfer = ""; + if (write_back) + transfer = "t"; + + if (shift_amount == 0) { + if (shift_type == 0) { + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", + opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); + } + if (shift_type == 3) { + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", + opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); + } + shift_amount = 32; + } + + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", + opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm, + shift_name, shift_amount); +} + +std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t is_load = (insn >> 20) & 0x1; + uint8_t write_back = (insn >> 21) & 0x1; + uint8_t is_immed = (insn >> 22) & 0x1; + uint8_t is_up = (insn >> 23) & 0x1; + uint8_t is_pre = (insn >> 24) & 0x1; + uint8_t rn = (insn >> 16) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint8_t bits_65 = (insn >> 5) & 0x3; + uint8_t rm = insn & 0xf; + uint8_t offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf); + + const char *opname = "ldr"; + if (is_load == 0) + opname = "str"; + + const char *width = ""; + if (bits_65 == 1) + width = "h"; + else if (bits_65 == 2) + width = "sb"; + else + width = "sh"; + + const char *bang = ""; + if (write_back) + bang = "!"; + const char *minus = ""; + if (is_up == 0) + minus = "-"; + + if (is_immed) { + if (is_pre) { + if (offset == 0) { + return Common::StringFromFormat("%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn); + } else { + return Common::StringFromFormat("%s%sh\tr%d, [r%d, #%s%u]%s", + opname, cond_to_str(cond), rd, rn, minus, offset, bang); + } + } else { + return Common::StringFromFormat("%s%sh\tr%d, [r%d], #%s%u", + opname, cond_to_str(cond), rd, rn, minus, offset); + } + } + + if (is_pre) { + return Common::StringFromFormat("%s%sh\tr%d, [r%d, %sr%d]%s", + opname, cond_to_str(cond), rd, rn, minus, rm, bang); + } else { + return Common::StringFromFormat("%s%sh\tr%d, [r%d], %sr%d", + opname, cond_to_str(cond), rd, rn, minus, rm); + } +} + +std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t crn = (insn >> 16) & 0xf; + uint8_t crd = (insn >> 12) & 0xf; + uint8_t cpnum = (insn >> 8) & 0xf; + uint8_t opcode2 = (insn >> 5) & 0x7; + uint8_t crm = insn & 0xf; + + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", + opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2); +} + +std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rd = (insn >> 16) & 0xf; + uint8_t rn = (insn >> 12) & 0xf; + uint8_t rs = (insn >> 8) & 0xf; + uint8_t rm = insn & 0xf; + uint8_t bit_s = (insn >> 20) & 1; + + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", + opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn); +} + +std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rdhi = (insn >> 16) & 0xf; + uint8_t rdlo = (insn >> 12) & 0xf; + uint8_t rs = (insn >> 8) & 0xf; + uint8_t rm = insn & 0xf; + uint8_t bit_s = (insn >> 20) & 1; + + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", + opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs); +} + +std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rd = (insn >> 16) & 0xf; + uint8_t rs = (insn >> 8) & 0xf; + uint8_t rm = insn & 0xf; + uint8_t bit_s = (insn >> 20) & 1; + + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", + opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs); +} + +std::string ARM_Disasm::DisassembleMRS(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint8_t ps = (insn >> 22) & 1; + + return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr"); +} + +std::string ARM_Disasm::DisassembleMSR(uint32_t insn) +{ + char flags[8]; + int flag_index = 0; + uint8_t cond = (insn >> 28) & 0xf; + uint8_t is_immed = (insn >> 25) & 0x1; + uint8_t pd = (insn >> 22) & 1; + uint8_t mask = (insn >> 16) & 0xf; + + if (mask & 1) + flags[flag_index++] = 'c'; + if (mask & 2) + flags[flag_index++] = 'x'; + if (mask & 4) + flags[flag_index++] = 's'; + if (mask & 8) + flags[flag_index++] = 'f'; + flags[flag_index] = 0; + + if (is_immed) { + uint32_t immed = insn & 0xff; + uint8_t rotate = (insn >> 8) & 0xf; + uint8_t rotate2 = rotate << 1; + uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2)); + return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", + cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val); + } + + uint8_t rm = insn & 0xf; + + return Common::StringFromFormat("msr%s\t%s_%s, r%d", + cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm); +} + +std::string ARM_Disasm::DisassemblePLD(uint32_t insn) +{ + uint8_t is_reg = (insn >> 25) & 0x1; + uint8_t is_up = (insn >> 23) & 0x1; + uint8_t rn = (insn >> 16) & 0xf; + + const char *minus = ""; + if (is_up == 0) + minus = "-"; + + if (is_reg) { + uint8_t rm = insn & 0xf; + return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm); + } + + uint16_t offset = insn & 0xfff; + if (offset == 0) { + return Common::StringFromFormat("pld\t[r%d]", rn); + } else { + return Common::StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset); + } +} + +std::string ARM_Disasm::DisassembleSWI(uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint32_t sysnum = insn & 0x00ffffff; + + return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum); +} + +std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn) +{ + uint8_t cond = (insn >> 28) & 0xf; + uint8_t rn = (insn >> 16) & 0xf; + uint8_t rd = (insn >> 12) & 0xf; + uint8_t rm = insn & 0xf; + + const char *opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn); +} + +Opcode ARM_Disasm::Decode(uint32_t insn) { + uint32_t bits27_26 = (insn >> 26) & 0x3; + switch (bits27_26) { + case 0x0: + return Decode00(insn); + case 0x1: + return Decode01(insn); + case 0x2: + return Decode10(insn); + case 0x3: + return Decode11(insn); + } + return OP_INVALID; +} + +Opcode ARM_Disasm::Decode00(uint32_t insn) { + uint8_t bit25 = (insn >> 25) & 0x1; + uint8_t bit4 = (insn >> 4) & 0x1; + if (bit25 == 0 && bit4 == 1) { + if ((insn & 0x0ffffff0) == 0x012fff10) { + // Bx instruction + return OP_BX; + } + if ((insn & 0x0ff000f0) == 0x01600010) { + // Clz instruction + return OP_CLZ; + } + if ((insn & 0xfff000f0) == 0xe1200070) { + // Bkpt instruction + return OP_BKPT; + } + uint32_t bits7_4 = (insn >> 4) & 0xf; + if (bits7_4 == 0x9) { + if ((insn & 0x0ff00ff0) == 0x01000090) { + // Swp instruction + uint8_t bit22 = (insn >> 22) & 0x1; + if (bit22) + return OP_SWPB; + return OP_SWP; + } + // One of the multiply instructions + return DecodeMUL(insn); + } + + uint8_t bit7 = (insn >> 7) & 0x1; + if (bit7 == 1) { + // One of the load/store halfword/byte instructions + return DecodeLDRH(insn); + } + } + + // One of the data processing instructions + return DecodeALU(insn); +} + +Opcode ARM_Disasm::Decode01(uint32_t insn) { + uint8_t is_reg = (insn >> 25) & 0x1; + uint8_t bit4 = (insn >> 4) & 0x1; + if (is_reg == 1 && bit4 == 1) + return OP_UNDEFINED; + uint8_t is_load = (insn >> 20) & 0x1; + uint8_t is_byte = (insn >> 22) & 0x1; + if ((insn & 0xfd70f000) == 0xf550f000) { + // Pre-load + return OP_PLD; + } + if (is_load) { + if (is_byte) { + // Load byte + return OP_LDRB; + } + // Load word + return OP_LDR; + } + if (is_byte) { + // Store byte + return OP_STRB; + } + // Store word + return OP_STR; +} + +Opcode ARM_Disasm::Decode10(uint32_t insn) { + uint8_t bit25 = (insn >> 25) & 0x1; + if (bit25 == 0) { + // LDM/STM + uint8_t is_load = (insn >> 20) & 0x1; + if (is_load) + return OP_LDM; + return OP_STM; + } + // Branch or Branch with link + uint8_t is_link = (insn >> 24) & 1; + uint32_t offset = insn & 0xffffff; + + // Sign-extend the 24-bit offset + if ((offset >> 23) & 1) + offset |= 0xff000000; + + // Pre-compute the left-shift and the prefetch offset + offset <<= 2; + offset += 8; + if (is_link == 0) + return OP_B; + return OP_BL; +} + +Opcode ARM_Disasm::Decode11(uint32_t insn) { + uint8_t bit25 = (insn >> 25) & 0x1; + if (bit25 == 0) { + // LDC, SDC + uint8_t is_load = (insn >> 20) & 0x1; + if (is_load) { + // LDC + return OP_LDC; + } + // STC + return OP_STC; + } + + uint8_t bit24 = (insn >> 24) & 0x1; + if (bit24 == 0x1) { + // SWI + return OP_SWI; + } + + uint8_t bit4 = (insn >> 4) & 0x1; + uint8_t cpnum = (insn >> 8) & 0xf; + + if (cpnum == 15) { + // Special case for coprocessor 15 + uint8_t opcode = (insn >> 21) & 0x7; + if (bit4 == 0 || opcode != 0) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + + // MRC, MCR + uint8_t is_mrc = (insn >> 20) & 0x1; + if (is_mrc) + return OP_MRC; + return OP_MCR; + } + + if (bit4 == 0) { + // CDP + return OP_CDP; + } + // MRC, MCR + uint8_t is_mrc = (insn >> 20) & 0x1; + if (is_mrc) + return OP_MRC; + return OP_MCR; +} + +Opcode ARM_Disasm::DecodeMUL(uint32_t insn) { + uint8_t bit24 = (insn >> 24) & 0x1; + if (bit24 != 0) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + uint8_t bit23 = (insn >> 23) & 0x1; + uint8_t bit22_U = (insn >> 22) & 0x1; + uint8_t bit21_A = (insn >> 21) & 0x1; + if (bit23 == 0) { + // 32-bit multiply + if (bit22_U != 0) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + if (bit21_A == 0) + return OP_MUL; + return OP_MLA; + } + // 64-bit multiply + if (bit22_U == 0) { + // Unsigned multiply long + if (bit21_A == 0) + return OP_UMULL; + return OP_UMLAL; + } + // Signed multiply long + if (bit21_A == 0) + return OP_SMULL; + return OP_SMLAL; +} + +Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) { + uint8_t is_load = (insn >> 20) & 0x1; + uint8_t bits_65 = (insn >> 5) & 0x3; + if (is_load) { + if (bits_65 == 0x1) { + // Load unsigned halfword + return OP_LDRH; + } else if (bits_65 == 0x2) { + // Load signed byte + return OP_LDRSB; + } + // Signed halfword + if (bits_65 != 0x3) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + // Load signed halfword + return OP_LDRSH; + } + // Store halfword + if (bits_65 != 0x1) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + // Store halfword + return OP_STRH; +} + +Opcode ARM_Disasm::DecodeALU(uint32_t insn) { + uint8_t is_immed = (insn >> 25) & 0x1; + uint8_t opcode = (insn >> 21) & 0xf; + uint8_t bit_s = (insn >> 20) & 1; + uint8_t shift_is_reg = (insn >> 4) & 1; + uint8_t bit7 = (insn >> 7) & 1; + if (!is_immed && shift_is_reg && (bit7 != 0)) { + // This is an unexpected bit pattern. Create an undefined + // instruction in case this is ever executed. + return OP_UNDEFINED; + } + switch (opcode) { + case 0x0: + return OP_AND; + case 0x1: + return OP_EOR; + case 0x2: + return OP_SUB; + case 0x3: + return OP_RSB; + case 0x4: + return OP_ADD; + case 0x5: + return OP_ADC; + case 0x6: + return OP_SBC; + case 0x7: + return OP_RSC; + case 0x8: + if (bit_s) + return OP_TST; + return OP_MRS; + case 0x9: + if (bit_s) + return OP_TEQ; + return OP_MSR; + case 0xa: + if (bit_s) + return OP_CMP; + return OP_MRS; + case 0xb: + if (bit_s) + return OP_CMN; + return OP_MSR; + case 0xc: + return OP_ORR; + case 0xd: + return OP_MOV; + case 0xe: + return OP_BIC; + case 0xf: + return OP_MVN; + } + // Unreachable + return OP_INVALID; +} diff --git a/source/arm/disassembler/arm_disasm.h b/source/arm/disassembler/arm_disasm.h new file mode 100644 index 0000000..f94bd46 --- /dev/null +++ b/source/arm/disassembler/arm_disasm.h @@ -0,0 +1,141 @@ +// Copyright 2006 The Android Open Source Project + +#pragma once + +#include +#include + +// Note: this list of opcodes must match the list used to initialize +// the opflags[] array in opcode.cpp. +enum Opcode { + OP_INVALID, + OP_UNDEFINED, + OP_ADC, + OP_ADD, + OP_AND, + OP_B, + OP_BL, + OP_BIC, + OP_BKPT, + OP_BLX, + OP_BX, + OP_CDP, + OP_CLZ, + OP_CMN, + OP_CMP, + OP_EOR, + OP_LDC, + OP_LDM, + OP_LDR, + OP_LDRB, + OP_LDRBT, + OP_LDRH, + OP_LDRSB, + OP_LDRSH, + OP_LDRT, + OP_MCR, + OP_MLA, + OP_MOV, + OP_MRC, + OP_MRS, + OP_MSR, + OP_MUL, + OP_MVN, + OP_ORR, + OP_PLD, + OP_RSB, + OP_RSC, + OP_SBC, + OP_SMLAL, + OP_SMULL, + OP_STC, + OP_STM, + OP_STR, + OP_STRB, + OP_STRBT, + OP_STRH, + OP_STRT, + OP_SUB, + OP_SWI, + OP_SWP, + OP_SWPB, + OP_TEQ, + OP_TST, + OP_UMLAL, + OP_UMULL, + + // Define thumb opcodes + OP_THUMB_UNDEFINED, + OP_THUMB_ADC, + OP_THUMB_ADD, + OP_THUMB_AND, + OP_THUMB_ASR, + OP_THUMB_B, + OP_THUMB_BIC, + OP_THUMB_BKPT, + OP_THUMB_BL, + OP_THUMB_BLX, + OP_THUMB_BX, + OP_THUMB_CMN, + OP_THUMB_CMP, + OP_THUMB_EOR, + OP_THUMB_LDMIA, + OP_THUMB_LDR, + OP_THUMB_LDRB, + OP_THUMB_LDRH, + OP_THUMB_LDRSB, + OP_THUMB_LDRSH, + OP_THUMB_LSL, + OP_THUMB_LSR, + OP_THUMB_MOV, + OP_THUMB_MUL, + OP_THUMB_MVN, + OP_THUMB_NEG, + OP_THUMB_ORR, + OP_THUMB_POP, + OP_THUMB_PUSH, + OP_THUMB_ROR, + OP_THUMB_SBC, + OP_THUMB_STMIA, + OP_THUMB_STR, + OP_THUMB_STRB, + OP_THUMB_STRH, + OP_THUMB_SUB, + OP_THUMB_SWI, + OP_THUMB_TST, + + OP_END // must be last +}; + +class ARM_Disasm { + public: + static std::string Disassemble(uint32_t addr, uint32_t insn); + static Opcode Decode(uint32_t insn); + + private: + static Opcode Decode00(uint32_t insn); + static Opcode Decode01(uint32_t insn); + static Opcode Decode10(uint32_t insn); + static Opcode Decode11(uint32_t insn); + static Opcode DecodeMUL(uint32_t insn); + static Opcode DecodeLDRH(uint32_t insn); + static Opcode DecodeALU(uint32_t insn); + + static std::string DisassembleALU(Opcode opcode, uint32_t insn); + static std::string DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn); + static std::string DisassembleBX(uint32_t insn); + static std::string DisassembleBKPT(uint32_t insn); + static std::string DisassembleCLZ(uint32_t insn); + static std::string DisassembleMemblock(Opcode opcode, uint32_t insn); + static std::string DisassembleMem(uint32_t insn); + static std::string DisassembleMemHalf(uint32_t insn); + static std::string DisassembleMCR(Opcode opcode, uint32_t insn); + static std::string DisassembleMLA(Opcode opcode, uint32_t insn); + static std::string DisassembleUMLAL(Opcode opcode, uint32_t insn); + static std::string DisassembleMUL(Opcode opcode, uint32_t insn); + static std::string DisassembleMRS(uint32_t insn); + static std::string DisassembleMSR(uint32_t insn); + static std::string DisassemblePLD(uint32_t insn); + static std::string DisassembleSWI(uint32_t insn); + static std::string DisassembleSWP(Opcode opcode, uint32_t insn); +}; diff --git a/source/arm/dyncom/arm_dyncom.cpp b/source/arm/dyncom/arm_dyncom.cpp new file mode 100644 index 0000000..e5b266e --- /dev/null +++ b/source/arm/dyncom/arm_dyncom.cpp @@ -0,0 +1,154 @@ +// Copyright 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +//massive fixed by ichfly XDS/3dmoo team + +#include "Kernel.h" + +#include "arm/skyeye_common/armcpu.h" +#include "arm/skyeye_common/armemu.h" +#include "arm/skyeye_common/vfp/vfp.h" + +#include "arm/dyncom/arm_dyncom.h" +#include "arm/dyncom/arm_dyncom_interpreter.h" +#include "arm/dyncom/arm_dyncom_run.h" + +//#define CACHE_BUFFER_SIZE (64 * 1024 * 2000) + + +const static cpu_config_t s_arm11_cpu_info = { + "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE +}; + +ARM_DynCom::ARM_DynCom() { + state = (ARMul_State*)malloc(sizeof(ARMul_State)); + + ARMul_NewState(state); + ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); + + state->abort_model = 0; + state->cpu = (cpu_config_t*)&s_arm11_cpu_info; + + state->bigendSig = LOW; + state->lateabtSig = LOW; + state->NirqSig = HIGH; + + // Reset the core to initial state + ARMul_Reset(state); + state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext + state->Emulate = RUN; + + // Switch to the desired privilege mode. + switch_mode(state, 0); + + state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack + state->Reg[15] = 0x00000000; +} + +ARM_DynCom::~ARM_DynCom() { +} + +void ARM_DynCom::SetPC(u32 pc) { + state->Reg[15] = pc; +} + +u32 ARM_DynCom::GetPC() const { + return state->Reg[15]; +} + +u32 ARM_DynCom::GetReg(int index) const { + return state->Reg[index]; +} + +void ARM_DynCom::SetReg(int index, u32 value) { + state->Reg[index] = value; +} + +u32 ARM_DynCom::GetCPSR() const { + return state->Cpsr; +} + +void ARM_DynCom::SetCPSR(u32 cpsr) { + state->Cpsr = cpsr; +} + +void ARM_DynCom::AddTicks(u64 ticks) { + down_count -= ticks; + //if (down_count < 0) + //CoreTiming::Advance(); //ichfly todo +} + +u64 ARM_DynCom::ExecuteInstructions(int num_instructions) { + state->NumInstrsToExecute = num_instructions; + + // Dyncom only breaks on instruction dispatch. This only happens on every instruction when + // executing one instruction at a time. Otherwise, if a block is being executed, more + // instructions may actually be executed than specified. + unsigned ticks_executed = InterpreterMainLoop(state); + AddTicks(ticks_executed); + return ticks_executed; +} + +void ARM_DynCom::SaveContext(ThreadContext& ctx) { + memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); + memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); + + ctx.sp = state->Reg[13]; + ctx.lr = state->Reg[14]; + ctx.pc = state->pc; + ctx.cpsr = state->Cpsr; + + ctx.fpscr = state->VFP[1]; + ctx.fpexc = state->VFP[2]; + + ctx.reg_15 = state->Reg[15]; + ctx.mode = state->NextInstr; + + //Dyncore + state->m_currentThread->m_owner->repretBuffersize = state->inst_buffsize; + state->m_currentThread->m_owner->repretBuffertop = state->inst_bufftop; + + ctx.NFlag = state->NFlag; + ctx.ZFlag = state->ZFlag; + ctx.CFlag = state->CFlag; + ctx.VFlag = state->VFlag; + ctx.IFFlags = state->IFFlags; + +} + +void ARM_DynCom::LoadContext(const ThreadContext& ctx) { + memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); + memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); + + state->Reg[13] = ctx.sp; + state->Reg[14] = ctx.lr; + state->pc = ctx.pc; + state->Cpsr = ctx.cpsr; + state->Mode = ctx.cpsr&0x1F; + + state->VFP[1] = ctx.fpscr; + state->VFP[2] = ctx.fpexc; + + state->Reg[15] = ctx.reg_15; + state->NextInstr = ctx.mode; + + //Dyncore + state->inst_buf = state->m_currentThread->m_owner->repretBuffer; + state->inst_buffsize = state->m_currentThread->m_owner->repretBuffersize; + state->inst_bufftop = state->m_currentThread->m_owner->repretBuffertop; + state->CreamCache = state->m_currentThread->m_owner->CreamCache; + + state->NFlag = ctx.NFlag; + state->ZFlag = ctx.ZFlag; + state->CFlag = ctx.CFlag; + state->VFlag = ctx.VFlag; + state->IFFlags = ctx.IFFlags; +} + +void ARM_DynCom::PrepareReschedule() { + state->NumInstrsToExecute = 0; +} +u64 ARM_DynCom::GetTicks() const { + return state->NumInstrs; +} \ No newline at end of file diff --git a/source/arm/dyncom/arm_dyncom.h b/source/arm/dyncom/arm_dyncom.h new file mode 100644 index 0000000..b9c6988 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom.h @@ -0,0 +1,91 @@ +// Copyright 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include + +#include "arm/arm_interface.h" +#include "arm/skyeye_common/armdefs.h" + +class ARM_DynCom final : virtual public ARM_Interface { +public: + + ARM_DynCom(); + ~ARM_DynCom(); + + /** + * Set the Program Counter to an address + * @param pc Address to set PC to + */ + void SetPC(u32 pc) override; + + /* + * Get the current Program Counter + * @return Returns current PC + */ + u32 GetPC() const override; + + /** + * Get an ARM register + * @param index Register index (0-15) + * @return Returns the value in the register + */ + u32 GetReg(int index) const override; + + /** + * Set an ARM register + * @param index Register index (0-15) + * @param value Value to set register to + */ + void SetReg(int index, u32 value) override; + + /** + * Get the current CPSR register + * @return Returns the value of the CPSR register + */ + u32 GetCPSR() const override; + + /** + * Set the current CPSR register + * @param cpsr Value to set CPSR to + */ + void SetCPSR(u32 cpsr) override; + + /** + * Returns the number of clock ticks since the last reset + * @return Returns number of clock ticks + */ + u64 GetTicks() const override; + + /** + * Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time) + * @param ticks Number of ticks to advance the CPU core + */ + void AddTicks(u64 ticks) override; + + /** + * Saves the current CPU context + * @param ctx Thread context to save + */ + void SaveContext(ThreadContext& ctx) override; + + /** + * Loads a CPU context + * @param ctx Thread context to load + */ + void LoadContext(const ThreadContext& ctx) override; + + /// Prepare core for thread reschedule (if needed to correctly handle state) + void PrepareReschedule() override; + + /** + * Executes the given number of instructions + * @param num_instructions Number of instructions to executes + */ + u64 ExecuteInstructions(int num_instructions) override; + ARMul_State* state; + +private: +}; diff --git a/source/arm/dyncom/arm_dyncom_dec.cpp b/source/arm/dyncom/arm_dyncom_dec.cpp new file mode 100644 index 0000000..c4ecfae --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_dec.cpp @@ -0,0 +1,459 @@ +// Copyright 2012 Michael Kang, 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +//massive fixed by ichfly XDS/3dmoo team + +#include "Kernel.h" + +#include "arm/skyeye_common/arm_regformat.h" +#include "arm/skyeye_common/armdefs.h" +#include "arm/dyncom/arm_dyncom_dec.h" + +#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) +#define BIT(s, n) ((s >> (n)) & 1) + +const ISEITEM arm_instruction[] = { + { "vmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }, + { "vmls", 7, ARMVFP2, 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 }, + { "vnmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 }, + { "vnmla", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }, + { "vnmls", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }, + { "vnmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }, + { "vmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }, + { "vadd", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }, + { "vsub", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }, + { "vdiv", 5, ARMVFP2, 23, 27, 0x1D, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }, + { "vmov(i)", 4, ARMVFP3, 23, 27, 0x1D, 20, 21, 0x3, 9, 11, 0x5, 4, 7, 0 }, + { "vmov(r)", 5, ARMVFP3, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 1, 4, 4, 0 }, + { "vabs", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 }, + { "vneg", 5, ARMVFP2, 23, 27, 0x1D, 17, 21, 0x18, 9, 11, 0x5, 6, 7, 1, 4, 4, 0 }, + { "vsqrt", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x31, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 }, + { "vcmp", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x34, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }, + { "vcmp2", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x35, 9, 11, 0x5, 0, 6, 0x40 }, + { "vcvt(bds)", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x37, 9, 11, 0x5, 6, 7, 3, 4, 4, 0 }, + { "vcvt(bff)", 6, ARMVFP3, 23, 27, 0x1D, 19, 21, 0x7, 17, 17, 0x1, 9, 11, 5, 6, 6, 1 }, + { "vcvt(bfi)", 5, ARMVFP2, 23, 27, 0x1D, 19, 21, 0x7, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }, + { "vmovbrs", 3, ARMVFP2, 21, 27, 0x70, 8, 11, 0xA, 0, 6, 0x10 }, + { "vmsr", 2, ARMVFP2, 20, 27, 0xEE, 0, 11, 0xA10 }, + { "vmovbrc", 4, ARMVFP2, 23, 27, 0x1C, 20, 20, 0x0, 8, 11, 0xB, 0, 4, 0x10 }, + { "vmrs", 2, ARMVFP2, 20, 27, 0xEF, 0, 11, 0xA10 }, + { "vmovbcr", 4, ARMVFP2, 24, 27, 0xE, 20, 20, 1, 8, 11, 0xB, 0, 4, 0x10 }, + { "vmovbrrss", 3, ARMVFP2, 21, 27, 0x62, 8, 11, 0xA, 4, 4, 1 }, + { "vmovbrrd", 3, ARMVFP2, 21, 27, 0x62, 6, 11, 0x2C, 4, 4, 1 }, + { "vstr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 0, 9, 11, 5 }, + { "vpush", 3, ARMVFP2, 23, 27, 0x1A, 16, 21, 0x2D, 9, 11, 5 }, + { "vstm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 0, 9, 11, 5 }, + { "vpop", 3, ARMVFP2, 23, 27, 0x19, 16, 21, 0x3D, 9, 11, 5 }, + { "vldr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 1, 9, 11, 5 }, + { "vldm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 1, 9, 11, 5 }, + + { "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 }, + { "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a }, + { "bkpt", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000007 }, + { "blx", 1, 3, 25, 31, 0x0000007d }, + { "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 }, + { "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f }, + { "setend", 2, 6, 16, 31, 0x0000f101, 4, 7, 0x00000000 }, + { "clrex", 1, 6, 0, 31, 0xf57ff01f }, + { "rev16", 2, 6, 16, 27, 0x000006bf, 4, 11, 0x000000fb }, + { "usad8", 3, 6, 20, 27, 0x00000078, 12, 15, 0x0000000f, 4, 7, 0x00000001 }, + { "sxtb", 2, 6, 16, 27, 0x000006af, 4, 7, 0x00000007 }, + { "uxtb", 2, 6, 16, 27, 0x000006ef, 4, 7, 0x00000007 }, + { "sxth", 2, 6, 16, 27, 0x000006bf, 4, 7, 0x00000007 }, + { "sxtb16", 2, 6, 16, 27, 0x0000068f, 4, 7, 0x00000007 }, + { "uxth", 2, 6, 16, 27, 0x000006ff, 4, 7, 0x00000007 }, + { "uxtb16", 2, 6, 16, 27, 0x000006cf, 4, 7, 0x00000007 }, + { "cpy", 2, 6, 20, 27, 0x0000001a, 4, 11, 0x00000000 }, + { "uxtab", 2, 6, 20, 27, 0x0000006e, 4, 9, 0x00000007 }, + { "ssub8", 2, 6, 20, 27, 0x00000061, 4, 7, 0x0000000f }, + { "shsub8", 2, 6, 20, 27, 0x00000063, 4, 7, 0x0000000f }, + { "ssubaddx", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000005 }, + { "strex", 2, 6, 20, 27, 0x00000018, 4, 7, 0x00000009 }, + { "strexb", 2, 7, 20, 27, 0x0000001c, 4, 7, 0x00000009 }, + { "swp", 2, 0, 20, 27, 0x00000010, 4, 7, 0x00000009 }, + { "swpb", 2, 0, 20, 27, 0x00000014, 4, 7, 0x00000009 }, + { "ssub16", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000007 }, + { "ssat16", 2, 6, 20, 27, 0x0000006a, 4, 7, 0x00000003 }, + { "shsubaddx", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000005 }, + { "qsubaddx", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000005 }, + { "shaddsubx", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000003 }, + { "shadd8", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000009 }, + { "shadd16", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000001 }, + { "sel", 2, 6, 20, 27, 0x00000068, 4, 7, 0x0000000b }, + { "saddsubx", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000003 }, + { "sadd8", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000009 }, + { "sadd16", 2, 6, 20, 27, 0x00000061, 4, 7, 0x00000001 }, + { "shsub16", 2, 6, 20, 27, 0x00000063, 4, 7, 0x00000007 }, + { "umaal", 2, 6, 20, 27, 0x00000004, 4, 7, 0x00000009 }, + { "uxtab16", 2, 6, 20, 27, 0x0000006c, 4, 7, 0x00000007 }, + { "usubaddx", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000005 }, + { "usub8", 2, 6, 20, 27, 0x00000065, 4, 7, 0x0000000f }, + { "usub16", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000007 }, + { "usat16", 2, 6, 20, 27, 0x0000006e, 4, 7, 0x00000003 }, + { "usada8", 2, 6, 20, 27, 0x00000078, 4, 7, 0x00000001 }, + { "uqsubaddx", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000005 }, + { "uqsub8", 2, 6, 20, 27, 0x00000066, 4, 7, 0x0000000f }, + { "uqsub16", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000007 }, + { "uqaddsubx", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000003 }, + { "uqadd8", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000009 }, + { "uqadd16", 2, 6, 20, 27, 0x00000066, 4, 7, 0x00000001 }, + { "sxtab", 2, 6, 20, 27, 0x0000006a, 4, 7, 0x00000007 }, + { "uhsubaddx", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000005 }, + { "uhsub8", 2, 6, 20, 27, 0x00000067, 4, 7, 0x0000000f }, + { "uhsub16", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000007 }, + { "uhaddsubx", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000003 }, + { "uhadd8", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000009 }, + { "uhadd16", 2, 6, 20, 27, 0x00000067, 4, 7, 0x00000001 }, + { "uaddsubx", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000003 }, + { "uadd8", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000009 }, + { "uadd16", 2, 6, 20, 27, 0x00000065, 4, 7, 0x00000001 }, + { "sxtah", 2, 6, 20, 27, 0x0000006b, 4, 7, 0x00000007 }, + { "sxtab16", 2, 6, 20, 27, 0x00000068, 4, 7, 0x00000007 }, + { "qadd8", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000009 }, + { "bxj", 2, 5, 20, 27, 0x00000012, 4, 7, 0x00000002 }, + { "clz", 2, 3, 20, 27, 0x00000016, 4, 7, 0x00000001 }, + { "uxtah", 2, 6, 20, 27, 0x0000006f, 4, 7, 0x00000007 }, + { "bx", 2, 2, 20, 27, 0x00000012, 4, 7, 0x00000001 }, + { "rev", 2, 6, 20, 27, 0x0000006b, 4, 7, 0x00000003 }, + { "blx", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000003 }, + { "revsh", 2, 6, 20, 27, 0x0000006f, 4, 7, 0x0000000b }, + { "qadd", 2, 4, 20, 27, 0x00000010, 4, 7, 0x00000005 }, + { "qadd16", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000001 }, + { "qaddsubx", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000003 }, + { "ldrex", 2, 0, 20, 27, 0x00000019, 4, 7, 0x00000009 }, + { "qdadd", 2, 4, 20, 27, 0x00000014, 4, 7, 0x00000005 }, + { "qdsub", 2, 4, 20, 27, 0x00000016, 4, 7, 0x00000005 }, + { "qsub", 2, 4, 20, 27, 0x00000012, 4, 7, 0x00000005 }, + { "ldrexb", 2, 7, 20, 27, 0x0000001d, 4, 7, 0x00000009 }, + { "qsub8", 2, 6, 20, 27, 0x00000062, 4, 7, 0x0000000f }, + { "qsub16", 2, 6, 20, 27, 0x00000062, 4, 7, 0x00000007 }, + { "smuad", 4, 6, 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001 }, + { "smmul", 4, 6, 20, 27, 0x00000075, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001 }, + { "smusd", 4, 6, 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000001, 4, 4, 0x00000001 }, + { "smlsd", 3, 6, 20, 27, 0x00000070, 6, 7, 0x00000001, 4, 4, 0x00000001 }, + { "smlsld", 3, 6, 20, 27, 0x00000074, 6, 7, 0x00000001, 4, 4, 0x00000001 }, + { "smmla", 3, 6, 20, 27, 0x00000075, 6, 7, 0x00000000, 4, 4, 0x00000001 }, + { "smmls", 3, 6, 20, 27, 0x00000075, 6, 7, 0x00000003, 4, 4, 0x00000001 }, + { "smlald", 3, 6, 20, 27, 0x00000074, 6, 7, 0x00000000, 4, 4, 0x00000001 }, + { "smlad", 3, 6, 20, 27, 0x00000070, 6, 7, 0x00000000, 4, 4, 0x00000001 }, + { "smlaw", 3, 4, 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000000 }, + { "smulw", 3, 4, 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000002 }, + { "pkhtb", 2, 6, 20, 27, 0x00000068, 4, 6, 0x00000005 }, + { "pkhbt", 2, 6, 20, 27, 0x00000068, 4, 6, 0x00000001 }, + { "smul", 3, 4, 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000 }, + { "smlalxy", 3, 4, 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000 }, + { "smla", 3, 4, 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000 }, + { "mcrr", 1, 6, 20, 27, 0x000000c4 }, + { "mrrc", 1, 6, 20, 27, 0x000000c5 }, + { "cmp", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000015 }, + { "tst", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000011 }, + { "teq", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000013 }, + { "cmn", 2, 0, 26, 27, 0x00000000, 20, 24, 0x00000017 }, + { "smull", 2, 0, 21, 27, 0x00000006, 4, 7, 0x00000009 }, + { "umull", 2, 0, 21, 27, 0x00000004, 4, 7, 0x00000009 }, + { "umlal", 2, 0, 21, 27, 0x00000005, 4, 7, 0x00000009 }, + { "smlal", 2, 0, 21, 27, 0x00000007, 4, 7, 0x00000009 }, + { "mul", 2, 0, 21, 27, 0x00000000, 4, 7, 0x00000009 }, + { "mla", 2, 0, 21, 27, 0x00000001, 4, 7, 0x00000009 }, + { "ssat", 2, 6, 21, 27, 0x00000035, 4, 5, 0x00000001 }, + { "usat", 2, 6, 21, 27, 0x00000037, 4, 5, 0x00000001 }, + { "mrs", 4, 0, 23, 27, 0x00000002, 20, 21, 0x00000000, 16, 19, 0x0000000f, 0, 11, 0x00000000 }, + { "msr", 3, 0, 23, 27, 0x00000002, 20, 21, 0x00000002, 4, 7, 0x00000000 }, + { "and", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000000 }, + { "bic", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000e }, + { "ldm", 3, 0, 25, 27, 0x00000004, 20, 22, 0x00000005, 15, 15, 0x00000000 }, + { "eor", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000001 }, + { "add", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000004 }, + { "rsb", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000003 }, + { "rsc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000007 }, + { "sbc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000006 }, + { "adc", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000005 }, + { "sub", 2, 0, 26, 27, 0x00000000, 21, 24, 0x00000002 }, + { "orr", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000c }, + { "mvn", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000f }, + { "mov", 2, 0, 26, 27, 0x00000000, 21, 24, 0x0000000d }, + { "stm", 2, 0, 25, 27, 0x00000004, 20, 22, 0x00000004 }, + { "ldm", 4, 0, 25, 27, 0x00000004, 22, 22, 0x00000001, 20, 20, 0x00000001, 15, 15, 0x00000001 }, + { "ldrsh", 3, 2, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000f }, + { "stm", 3, 0, 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000000 }, + { "ldm", 3, 0, 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000001 }, + { "ldrsb", 3, 2, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000d }, + { "strd", 3, 4, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000f }, + { "ldrh", 3, 0, 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000b }, + { "strh", 3, 0, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000b }, + { "ldrd", 3, 4, 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000d }, + { "strt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000002 }, + { "strbt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000006 }, + { "ldrbt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000007 }, + { "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 }, + { "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 }, + { "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 }, + { "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 }, + { "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 }, + { "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 }, + { "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 }, + { "ldrcond", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 }, + { "str", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000000 }, + { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, + { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, + { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, + { "swi", 1, 0, 24, 27, 0x0000000f }, + { "bbl", 1, 0, 25, 27, 0x00000005 }, + { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, + { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, + { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, + { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, +}; + +const ISEITEM arm_exclusion_code[] = { + { "vmla", 0, ARMVFP2, 0 }, + { "vmls", 0, ARMVFP2, 0 }, + { "vnmla", 0, ARMVFP2, 0 }, + { "vnmla", 0, ARMVFP2, 0 }, + { "vnmls", 0, ARMVFP2, 0 }, + { "vnmul", 0, ARMVFP2, 0 }, + { "vmul", 0, ARMVFP2, 0 }, + { "vadd", 0, ARMVFP2, 0 }, + { "vsub", 0, ARMVFP2, 0 }, + { "vdiv", 0, ARMVFP2, 0 }, + { "vmov(i)", 0, ARMVFP3, 0 }, + { "vmov(r)", 0, ARMVFP3, 0 }, + { "vabs", 0, ARMVFP2, 0 }, + { "vneg", 0, ARMVFP2, 0 }, + { "vsqrt", 0, ARMVFP2, 0 }, + { "vcmp", 0, ARMVFP2, 0 }, + { "vcmp2", 0, ARMVFP2, 0 }, + { "vcvt(bff)", 0, ARMVFP3, 4, 4, 1 }, + { "vcvt(bds)", 0, ARMVFP2, 0 }, + { "vcvt(bfi)", 0, ARMVFP2, 0 }, + { "vmovbrs", 0, ARMVFP2, 0 }, + { "vmsr", 0, ARMVFP2, 0 }, + { "vmovbrc", 0, ARMVFP2, 0 }, + { "vmrs", 0, ARMVFP2, 0 }, + { "vmovbcr", 0, ARMVFP2, 0 }, + { "vmovbrrss", 0, ARMVFP2, 0 }, + { "vmovbrrd", 0, ARMVFP2, 0 }, + { "vstr", 0, ARMVFP2, 0 }, + { "vpush", 0, ARMVFP2, 0 }, + { "vstm", 0, ARMVFP2, 0 }, + { "vpop", 0, ARMVFP2, 0 }, + { "vldr", 0, ARMVFP2, 0 }, + { "vldm", 0, ARMVFP2, 0 }, + + { "srs", 0, 6, 0 }, + { "rfe", 0, 6, 0 }, + { "bkpt", 0, 3, 0 }, + { "blx", 0, 3, 0 }, + { "cps", 0, 6, 0 }, + { "pld", 0, 4, 0 }, + { "setend", 0, 6, 0 }, + { "clrex", 0, 6, 0 }, + { "rev16", 0, 6, 0 }, + { "usad8", 0, 6, 0 }, + { "sxtb", 0, 6, 0 }, + { "uxtb", 0, 6, 0 }, + { "sxth", 0, 6, 0 }, + { "sxtb16", 0, 6, 0 }, + { "uxth", 0, 6, 0 }, + { "uxtb16", 0, 6, 0 }, + { "cpy", 0, 6, 0 }, + { "uxtab", 0, 6, 0 }, + { "ssub8", 0, 6, 0 }, + { "shsub8", 0, 6, 0 }, + { "ssubaddx", 0, 6, 0 }, + { "strex", 0, 6, 0 }, + { "strexb", 0, 7, 0 }, + { "swp", 0, 0, 0 }, + { "swpb", 0, 0, 0 }, + { "ssub16", 0, 6, 0 }, + { "ssat16", 0, 6, 0 }, + { "shsubaddx", 0, 6, 0 }, + { "qsubaddx", 0, 6, 0 }, + { "shaddsubx", 0, 6, 0 }, + { "shadd8", 0, 6, 0 }, + { "shadd16", 0, 6, 0 }, + { "sel", 0, 6, 0 }, + { "saddsubx", 0, 6, 0 }, + { "sadd8", 0, 6, 0 }, + { "sadd16", 0, 6, 0 }, + { "shsub16", 0, 6, 0 }, + { "umaal", 0, 6, 0 }, + { "uxtab16", 0, 6, 0 }, + { "usubaddx", 0, 6, 0 }, + { "usub8", 0, 6, 0 }, + { "usub16", 0, 6, 0 }, + { "usat16", 0, 6, 0 }, + { "usada8", 0, 6, 0 }, + { "uqsubaddx", 0, 6, 0 }, + { "uqsub8", 0, 6, 0 }, + { "uqsub16", 0, 6, 0 }, + { "uqaddsubx", 0, 6, 0 }, + { "uqadd8", 0, 6, 0 }, + { "uqadd16", 0, 6, 0 }, + { "sxtab", 0, 6, 0 }, + { "uhsubaddx", 0, 6, 0 }, + { "uhsub8", 0, 6, 0 }, + { "uhsub16", 0, 6, 0 }, + { "uhaddsubx", 0, 6, 0 }, + { "uhadd8", 0, 6, 0 }, + { "uhadd16", 0, 6, 0 }, + { "uaddsubx", 0, 6, 0 }, + { "uadd8", 0, 6, 0 }, + { "uadd16", 0, 6, 0 }, + { "sxtah", 0, 6, 0 }, + { "sxtab16", 0, 6, 0 }, + { "qadd8", 0, 6, 0 }, + { "bxj", 0, 5, 0 }, + { "clz", 0, 3, 0 }, + { "uxtah", 0, 6, 0 }, + { "bx", 0, 2, 0 }, + { "rev", 0, 6, 0 }, + { "blx", 0, 3, 0 }, + { "revsh", 0, 6, 0 }, + { "qadd", 0, 4, 0 }, + { "qadd16", 0, 6, 0 }, + { "qaddsubx", 0, 6, 0 }, + { "ldrex", 0, 0, 0 }, + { "qdadd", 0, 4, 0 }, + { "qdsub", 0, 4, 0 }, + { "qsub", 0, 4, 0 }, + { "ldrexb", 0, 7, 0 }, + { "qsub8", 0, 6, 0 }, + { "qsub16", 0, 6, 0 }, + { "smuad", 0, 6, 0 }, + { "smmul", 0, 6, 0 }, + { "smusd", 0, 6, 0 }, + { "smlsd", 0, 6, 0 }, + { "smlsld", 0, 6, 0 }, + { "smmla", 0, 6, 0 }, + { "smmls", 0, 6, 0 }, + { "smlald", 0, 6, 0 }, + { "smlad", 0, 6, 0 }, + { "smlaw", 0, 4, 0 }, + { "smulw", 0, 4, 0 }, + { "pkhtb", 0, 6, 0 }, + { "pkhbt", 0, 6, 0 }, + { "smul", 0, 4, 0 }, + { "smlal", 0, 4, 0 }, + { "smla", 0, 4, 0 }, + { "mcrr", 0, 6, 0 }, + { "mrrc", 0, 6, 0 }, + { "cmp", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "tst", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "teq", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "cmn", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "smull", 0, 0, 0 }, + { "umull", 0, 0, 0 }, + { "umlal", 0, 0, 0 }, + { "smlal", 0, 0, 0 }, + { "mul", 0, 0, 0 }, + { "mla", 0, 0, 0 }, + { "ssat", 0, 6, 0 }, + { "usat", 0, 6, 0 }, + { "mrs", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "and", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "bic", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "ldm", 0, 0, 0 }, + { "eor", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "add", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "rsb", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "rsc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "sbc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "adc", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "sub", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "orr", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "mvn", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "mov", 3, 0, 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000 }, + { "stm", 0, 0, 0 }, + { "ldm", 0, 0, 0 }, + { "ldrsh", 0, 2, 0 }, + { "stm", 0, 0, 0 }, + { "ldm", 0, 0, 0 }, + { "ldrsb", 0, 2, 0 }, + { "strd", 0, 4, 0 }, + { "ldrh", 0, 0, 0 }, + { "strh", 0, 0, 0 }, + { "ldrd", 0, 4, 0 }, + { "strt", 0, 0, 0 }, + { "strbt", 0, 0, 0 }, + { "ldrbt", 0, 0, 0 }, + { "ldrt", 0, 0, 0 }, + { "mrc", 0, 6, 0 }, + { "mcr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "ldrb", 0, 0, 0 }, + { "strb", 0, 0, 0 }, + { "ldr", 0, 0, 0 }, + { "ldrcond", 1, 0, 28, 31, 0x0000000e }, + { "str", 0, 0, 0 }, + { "cdp", 0, 0, 0 }, + { "stc", 0, 0, 0 }, + { "ldc", 0, 0, 0 }, + { "swi", 0, 0, 0 }, + { "bbl", 0, 0, 0 }, + { "ldrexd", 0, ARMV6K, 0 }, + { "strexd", 0, ARMV6K, 0 }, + { "ldrexh", 0, ARMV6K, 0 }, + { "strexh", 0, ARMV6K, 0 }, + + { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] + { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] + { "blx_1_thumb", 0, INVALID, 0 }, // Should be located at table[-2] + { "invalid", 0, INVALID, 0 } +}; + +int decode_arm_instr(uint32_t instr, int32_t *idx) { + int n = 0; + int base = 0; + int ret = DECODE_FAILURE; + int i = 0; + int instr_slots = sizeof(arm_instruction) / sizeof(ISEITEM); + + for (i = 0; i < instr_slots; i++) { + n = arm_instruction[i].attribute_value; + base = 0; + + while (n) { + if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) { + // clrex + if (instr != arm_instruction[i].content[base + 2]) { + break; + } + } else if (BITS(instr, arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { + break; + } + base += 3; + n--; + } + + // All conditions is satisfied. + if (n == 0) + ret = DECODE_SUCCESS; + + if (ret == DECODE_SUCCESS) { + n = arm_exclusion_code[i].attribute_value; + if (n != 0) { + base = 0; + while (n) { + if (BITS(instr, arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { + break; + } + base += 3; + n--; + } + + // All conditions is satisfied. + if (n == 0) + ret = DECODE_FAILURE; + } + } + + if (ret == DECODE_SUCCESS) { + *idx = i; + return ret; + } + } + return ret; +} diff --git a/source/arm/dyncom/arm_dyncom_dec.h b/source/arm/dyncom/arm_dyncom_dec.h new file mode 100644 index 0000000..4b5f5ad --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_dec.h @@ -0,0 +1,39 @@ +// Copyright 2012 Michael Kang, 2015 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +int decode_arm_instr(uint32_t instr, int32_t *idx); + +enum DECODE_STATUS { + DECODE_SUCCESS, + DECODE_FAILURE +}; + +struct instruction_set_encoding_item { + const char *name; + int attribute_value; + int version; + u32 content[21]; +}; + +typedef struct instruction_set_encoding_item ISEITEM; + +// ARM versions +enum { + INVALID = 0, + ARMALL, + ARMV4, + ARMV4T, + ARMV5T, + ARMV5TE, + ARMV5TEJ, + ARMV6, + ARM1176JZF_S, + ARMVFP2, + ARMVFP3, + ARMV6K, +}; + +extern const ISEITEM arm_instruction[]; diff --git a/source/arm/dyncom/arm_dyncom_interpreter.cpp b/source/arm/dyncom/arm_dyncom_interpreter.cpp new file mode 100644 index 0000000..2c3474b --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_interpreter.cpp @@ -0,0 +1,6957 @@ +// Copyright 2012 Michael Kang, 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +//massive fixed by ichfly XDS/3dmoo team + +//#define inst_debug +#define LOGMODULE "fs" + +#include "Kernel.h" +#define CITRA_IGNORE_EXIT(x) + +#include +#include +#include +#include +#include +#include + +using namespace std; + +#include "Common.h" + + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armmmu.h" +#include "arm_dyncom_thumb.h" +#include "arm_dyncom_run.h" +#include "arm/skyeye_common/vfp/vfp.h" +#include "arm/disassembler/arm_disasm.h" + +#include "arm/memory.h" + +enum { + COND = (1 << 0), + NON_BRANCH = (1 << 1), + DIRECT_BRANCH = (1 << 2), + INDIRECT_BRANCH = (1 << 3), + CALL = (1 << 4), + RET = (1 << 5), + END_OF_PAGE = (1 << 6), + THUMB = (1 << 7) +}; + + +#undef BITS +#undef BIT +#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) +#define BIT(s, n) ((s >> (n)) & 1) + +#define RM BITS(sht_oper, 0, 3) +#define RS BITS(sht_oper, 8, 11) + +#define glue(x, y) x ## y +#define DPO(s) glue(DataProcessingOperands, s) +#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i)) +#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) +#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32) +#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) + +#define rotr(x,n) ( (x >> n) | ((x & ((1 << (n + 1)) - 1)) << (32 - n)) ) + +extern void switch_mode(arm_core_t *core, uint32_t mode); + +typedef arm_core_t arm_processor; +typedef unsigned int(*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper); + +typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); + +// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag. +// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to +// support LDR/STREXD. +static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8; + +// Exclusive memory access +static int exclusive_detect(ARMul_State* state, ARMword addr) { + if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK)) + return 0; + else + return -1; +} + +static void add_exclusive_addr(ARMul_State* state, ARMword addr){ + state->exclusive_tag = addr & RESERVATION_GRANULE_MASK; + return; +} + +static void remove_exclusive(ARMul_State* state, ARMword addr){ + state->exclusive_tag = 0xFFFFFFFF; +} + +static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int immed_8 = BITS(sht_oper, 0, 7); + unsigned int rotate_imm = BITS(sht_oper, 8, 11); + unsigned int shifter_operand = ROTATE_RIGHT_32(immed_8, rotate_imm * 2); + if (rotate_imm == 0) + cpu->shifter_carry_out = cpu->CFlag; + else + cpu->shifter_carry_out = BIT(shifter_operand, 31); + return shifter_operand; +} + +static unsigned int DPO(Register)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + return shifter_operand; +} + +static unsigned int DPO(LogicalShiftLeftByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { + int shift_imm = BITS(sht_oper, 7, 11); + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand; + if (shift_imm == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + } else { + shifter_operand = rm << shift_imm; + cpu->shifter_carry_out = BIT(rm, 32 - shift_imm); + } + return shifter_operand; +} + +static unsigned int DPO(LogicalShiftLeftByRegister)(ARMul_State* cpu, unsigned int sht_oper) { + int shifter_operand; + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int rs = CHECK_READ_REG15(cpu, RS); + if (BITS(rs, 0, 7) == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + } else if (BITS(rs, 0, 7) < 32) { + shifter_operand = rm << BITS(rs, 0, 7); + cpu->shifter_carry_out = BIT(rm, 32 - BITS(rs, 0, 7)); + } else if (BITS(rs, 0, 7) == 32) { + shifter_operand = 0; + cpu->shifter_carry_out = BIT(rm, 0); + } else { + shifter_operand = 0; + cpu->shifter_carry_out = 0; + } + return shifter_operand; +} + +static unsigned int DPO(LogicalShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand; + int shift_imm = BITS(sht_oper, 7, 11); + if (shift_imm == 0) { + shifter_operand = 0; + cpu->shifter_carry_out = BIT(rm, 31); + } else { + shifter_operand = rm >> shift_imm; + cpu->shifter_carry_out = BIT(rm, shift_imm - 1); + } + return shifter_operand; +} + +static unsigned int DPO(LogicalShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rs = CHECK_READ_REG15(cpu, RS); + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand; + if (BITS(rs, 0, 7) == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + } else if (BITS(rs, 0, 7) < 32) { + shifter_operand = rm >> BITS(rs, 0, 7); + cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 7) - 1); + } else if (BITS(rs, 0, 7) == 32) { + shifter_operand = 0; + cpu->shifter_carry_out = BIT(rm, 31); + } else { + shifter_operand = 0; + cpu->shifter_carry_out = 0; + } + return shifter_operand; +} + +static unsigned int DPO(ArithmeticShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand; + int shift_imm = BITS(sht_oper, 7, 11); + if (shift_imm == 0) { + if (BIT(rm, 31) == 0) + shifter_operand = 0; + else + shifter_operand = 0xFFFFFFFF; + cpu->shifter_carry_out = BIT(rm, 31); + } else { + shifter_operand = static_cast(rm) >> shift_imm; + cpu->shifter_carry_out = BIT(rm, shift_imm - 1); + } + return shifter_operand; +} + +static unsigned int DPO(ArithmeticShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rs = CHECK_READ_REG15(cpu, RS); + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int shifter_operand; + if (BITS(rs, 0, 7) == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + } else if (BITS(rs, 0, 7) < 32) { + shifter_operand = static_cast(rm) >> BITS(rs, 0, 7); + cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 7) - 1); + } else { + if (BIT(rm, 31) == 0) + shifter_operand = 0; + else + shifter_operand = 0xffffffff; + cpu->shifter_carry_out = BIT(rm, 31); + } + return shifter_operand; +} + +static unsigned int DPO(RotateRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int shifter_operand; + unsigned int rm = CHECK_READ_REG15(cpu, RM); + int shift_imm = BITS(sht_oper, 7, 11); + if (shift_imm == 0) { + shifter_operand = (cpu->CFlag << 31) | (rm >> 1); + cpu->shifter_carry_out = BIT(rm, 0); + } else { + shifter_operand = ROTATE_RIGHT_32(rm, shift_imm); + cpu->shifter_carry_out = BIT(rm, shift_imm - 1); + } + return shifter_operand; +} + +static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { + unsigned int rm = CHECK_READ_REG15(cpu, RM); + unsigned int rs = CHECK_READ_REG15(cpu, RS); + unsigned int shifter_operand; + if (BITS(rs, 0, 7) == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = cpu->CFlag; + } else if (BITS(rs, 0, 4) == 0) { + shifter_operand = rm; + cpu->shifter_carry_out = BIT(rm, 31); + } else { + shifter_operand = ROTATE_RIGHT_32(rm, BITS(rs, 0, 4)); + cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 4) - 1); + } + return shifter_operand; +} + +typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw); + +typedef struct _ldst_inst { + unsigned int inst; + get_addr_fp_t get_addr; +} ldst_inst; +#define DEBUG_MSG LOG("inst is %x", inst); CITRA_IGNORE_EXIT(0) + +int CondPassed(ARMul_State* cpu, unsigned int cond); + +#define LnSWoUB(s) glue(LnSWoUB, s) +#define MLnS(s) glue(MLnS, s) +#define LdnStM(s) glue(LdnStM, s) + +#define W_BIT BIT(inst, 21) +#define U_BIT BIT(inst, 23) +#define I_BIT BIT(inst, 25) +#define P_BIT BIT(inst, 24) +#define OFFSET_12 BITS(inst, 0, 11) + +static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int addr; + + if (U_BIT) + addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12; + else + addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12; + + virt_addr = addr; +} + +static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + unsigned int addr; + + if (U_BIT) + addr = rn + rm; + else + addr = rn - rm; + + virt_addr = addr; +} + +static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); + + if (U_BIT) + cpu->Reg[Rn] += OFFSET_12; + else + cpu->Reg[Rn] -= OFFSET_12; + + virt_addr = addr; +} + +static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int addr; + + if (U_BIT) + addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12; + else + addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12; + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) + cpu->Reg[Rn] = addr; +} + +static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int addr; + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + + if (U_BIT) + addr = rn + rm; + else + addr = rn - rm; + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) + cpu->Reg[Rn] = addr; +} + +static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + unsigned int addr; + + if (U_BIT) + addr = rn + rm; + else + addr = rn - rm; + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) { + cpu->Reg[Rn] = addr; + } +} + +static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int shift = BITS(inst, 5, 6); + unsigned int shift_imm = BITS(inst, 7, 11); + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int index; + unsigned int addr; + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + + switch (shift) { + case 0: + index = rm << shift_imm; + break; + case 1: + if (shift_imm == 0) { + index = 0; + } else { + index = rm >> shift_imm; + } + break; + case 2: + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) + index = 0xFFFFFFFF; + else + index = 0; + } else { + index = static_cast(rm) >> shift_imm; + } + break; + case 3: + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } + break; + } + + if (U_BIT) + addr = rn + index; + else + addr = rn - index; + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) + cpu->Reg[Rn] = addr; +} + +static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int shift = BITS(inst, 5, 6); + unsigned int shift_imm = BITS(inst, 7, 11); + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int index; + unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + + switch (shift) { + case 0: + index = rm << shift_imm; + break; + case 1: + if (shift_imm == 0) { + index = 0; + } else { + index = rm >> shift_imm; + } + break; + case 2: + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) + index = 0xFFFFFFFF; + else + index = 0; + } else { + index = static_cast(rm) >> shift_imm; + } + break; + case 3: + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } + break; + } + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) { + if (U_BIT) + cpu->Reg[Rn] += index; + else + cpu->Reg[Rn] -= index; + } +} + +static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + + virt_addr = CHECK_READ_REG15_WA(cpu, Rn); + + if (CondPassed(cpu, BITS(inst, 28, 31))) { + if (U_BIT) { + cpu->Reg[Rn] += rm; + } else { + cpu->Reg[Rn] -= rm; + } + } +} + +static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int immedL = BITS(inst, 0, 3); + unsigned int immedH = BITS(inst, 8, 11); + unsigned int Rn = BITS(inst, 16, 19); + unsigned int addr; + + unsigned int offset_8 = (immedH << 4) | immedL; + + if (U_BIT) + addr = CHECK_READ_REG15_WA(cpu, Rn) + offset_8; + else + addr = CHECK_READ_REG15_WA(cpu, Rn) - offset_8; + + virt_addr = addr; +} + +static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int addr; + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + + if (U_BIT) + addr = rn + rm; + else + addr = rn - rm; + + virt_addr = addr; +} + +static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int immedH = BITS(inst, 8, 11); + unsigned int immedL = BITS(inst, 0, 3); + unsigned int addr; + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int offset_8 = (immedH << 4) | immedL; + + if (U_BIT) + addr = rn + offset_8; + else + addr = rn - offset_8; + + virt_addr = addr; + + if (CondPassed(cpu, BITS(inst, 28, 31))) + cpu->Reg[Rn] = addr; +} + +static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int immedH = BITS(inst, 8, 11); + unsigned int immedL = BITS(inst, 0, 3); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + + virt_addr = rn; + + if (CondPassed(cpu, BITS(inst, 28, 31))) { + unsigned int offset_8 = (immedH << 4) | immedL; + if (U_BIT) + rn += offset_8; + else + rn -= offset_8; + + cpu->Reg[Rn] = rn; + } +} + +static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + + virt_addr = CHECK_READ_REG15_WA(cpu, Rn); + + if (CondPassed(cpu, BITS(inst, 28, 31))) { + if (U_BIT) + cpu->Reg[Rn] += rm; + else + cpu->Reg[Rn] -= rm; + } +} + +static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int i = BITS(inst, 0, 15); + int count = 0; + + while (i) { + if (i & 1) count++; + i = i >> 1; + } + + virt_addr = CHECK_READ_REG15_WA(cpu, Rn) - count * 4; + + if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) + cpu->Reg[Rn] -= count * 4; +} + +static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int i = BITS(inst, 0, 15); + int count = 0; + + while (i) { + if (i & 1) count++; + i = i >> 1; + } + + virt_addr = CHECK_READ_REG15_WA(cpu, Rn) + 4; + + if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) + cpu->Reg[Rn] += count * 4; +} + +static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int i = BITS(inst, 0, 15); + int count = 0; + + while(i) { + if (i & 1) count++; + i = i >> 1; + } + + virt_addr = CHECK_READ_REG15_WA(cpu, Rn); + + if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) + cpu->Reg[Rn] += count * 4; +} + +static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int i = BITS(inst, 0, 15); + int count = 0; + while(i) { + if(i & 1) count++; + i = i >> 1; + } + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + unsigned int start_addr = rn - count * 4 + 4; + + virt_addr = start_addr; + + if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { + cpu->Reg[Rn] -= count * 4; + } +} + +static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { + unsigned int shift = BITS(inst, 5, 6); + unsigned int shift_imm = BITS(inst, 7, 11); + unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rm = BITS(inst, 0, 3); + unsigned int index; + unsigned int addr; + unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); + unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); + + switch (shift) { + case 0: + index = rm << shift_imm; + break; + case 1: + if (shift_imm == 0) { + index = 0; + } else { + index = rm >> shift_imm; + } + break; + case 2: + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) + index = 0xFFFFFFFF; + else + index = 0; + } else { + index = static_cast(rm) >> shift_imm; + } + break; + case 3: + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } + break; + } + + if (U_BIT) { + addr = rn + index; + } else + addr = rn - index; + + virt_addr = addr; +} + +typedef struct _arm_inst { + unsigned int idx; + unsigned int cond; + int br; + int load_r15; + char component[0]; +} arm_inst; + +typedef struct generic_arm_inst { + u32 Ra; + u32 Rm; + u32 Rn; + u32 Rd; + u8 op1; + u8 op2; +} generic_arm_inst; + +typedef struct _adc_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} adc_inst; + +typedef struct _add_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} add_inst; + +typedef struct _orr_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} orr_inst; + +typedef struct _and_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} and_inst; + +typedef struct _eor_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} eor_inst; + +typedef struct _bbl_inst { + unsigned int L; + int signed_immed_24; + unsigned int next_addr; + unsigned int jmp_addr; +} bbl_inst; + +typedef struct _bx_inst { + unsigned int Rm; +} bx_inst; + +typedef struct _blx_inst { + union { + int32_t signed_immed_24; + uint32_t Rm; + } val; + unsigned int inst; +} blx_inst; + +typedef struct _clz_inst { + unsigned int Rm; + unsigned int Rd; +} clz_inst; + +typedef struct _cps_inst { + unsigned int imod0; + unsigned int imod1; + unsigned int mmod; + unsigned int A, I, F; + unsigned int mode; +} cps_inst; + +typedef struct _clrex_inst { +} clrex_inst; + +typedef struct _cpy_inst { + unsigned int Rm; + unsigned int Rd; +} cpy_inst; + +typedef struct _bic_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} bic_inst; + +typedef struct _sub_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} sub_inst; + +typedef struct _tst_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} tst_inst; + +typedef struct _cmn_inst { + unsigned int I; + unsigned int Rn; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} cmn_inst; + +typedef struct _teq_inst { + unsigned int I; + unsigned int Rn; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} teq_inst; + +typedef struct _stm_inst { + unsigned int inst; +} stm_inst; + +struct bkpt_inst { + u32 imm; +}; + +struct blx1_inst { + unsigned int addr; +}; + +struct blx2_inst { + unsigned int Rm; +}; + +typedef struct _stc_inst { +} stc_inst; + +typedef struct _ldc_inst { +} ldc_inst; + +typedef struct _swi_inst { + unsigned int num; +} swi_inst; + +typedef struct _cmp_inst { + unsigned int I; + unsigned int Rn; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} cmp_inst; + +typedef struct _mov_inst { + unsigned int I; + unsigned int S; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} mov_inst; + +typedef struct _mvn_inst { + unsigned int I; + unsigned int S; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} mvn_inst; + +typedef struct _rev_inst { + unsigned int Rd; + unsigned int Rm; + unsigned int op1; + unsigned int op2; +} rev_inst; + +typedef struct _rsb_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} rsb_inst; + +typedef struct _rsc_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} rsc_inst; + +typedef struct _sbc_inst { + unsigned int I; + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int shifter_operand; + shtop_fp_t shtop_func; +} sbc_inst; + +typedef struct _mul_inst { + unsigned int S; + unsigned int Rd; + unsigned int Rs; + unsigned int Rm; +} mul_inst; + +typedef struct _smul_inst { + unsigned int Rd; + unsigned int Rs; + unsigned int Rm; + unsigned int x; + unsigned int y; +} smul_inst; + +typedef struct _umull_inst { + unsigned int S; + unsigned int RdHi; + unsigned int RdLo; + unsigned int Rs; + unsigned int Rm; +} umull_inst; +typedef struct _smlad_inst { + unsigned int m; + unsigned int Rm; + unsigned int Rd; + unsigned int Ra; + unsigned int Rn; + unsigned int op1; + unsigned int op2; +} smlad_inst; + +typedef struct _smla_inst { + unsigned int x; + unsigned int y; + unsigned int Rm; + unsigned int Rd; + unsigned int Rs; + unsigned int Rn; +} smla_inst; + +typedef struct smlalxy_inst { + unsigned int x; + unsigned int y; + unsigned int RdLo; + unsigned int RdHi; + unsigned int Rm; + unsigned int Rn; +} smlalxy_inst; + +typedef struct ssat_inst { + unsigned int Rn; + unsigned int Rd; + unsigned int imm5; + unsigned int sat_imm; + unsigned int shift_type; +} ssat_inst; + +typedef struct umaal_inst { + unsigned int Rn; + unsigned int Rm; + unsigned int RdHi; + unsigned int RdLo; +} umaal_inst; + +typedef struct _umlal_inst { + unsigned int S; + unsigned int Rm; + unsigned int Rs; + unsigned int RdHi; + unsigned int RdLo; +} umlal_inst; + +typedef struct _smlal_inst { + unsigned int S; + unsigned int Rm; + unsigned int Rs; + unsigned int RdHi; + unsigned int RdLo; +} smlal_inst; + +typedef struct smlald_inst { + unsigned int RdLo; + unsigned int RdHi; + unsigned int Rm; + unsigned int Rn; + unsigned int swap; + unsigned int op1; + unsigned int op2; +} smlald_inst; + +typedef struct _mla_inst { + unsigned int S; + unsigned int Rn; + unsigned int Rd; + unsigned int Rs; + unsigned int Rm; +} mla_inst; + +typedef struct _mrc_inst { + unsigned int opcode_1; + unsigned int opcode_2; + unsigned int cp_num; + unsigned int crn; + unsigned int crm; + unsigned int Rd; + unsigned int inst; +} mrc_inst; + +typedef struct _mcr_inst { + unsigned int opcode_1; + unsigned int opcode_2; + unsigned int cp_num; + unsigned int crn; + unsigned int crm; + unsigned int Rd; + unsigned int inst; +} mcr_inst; + +typedef struct _mrs_inst { + unsigned int R; + unsigned int Rd; +} mrs_inst; + +typedef struct _msr_inst { + unsigned int field_mask; + unsigned int R; + unsigned int inst; +} msr_inst; + +typedef struct _pld_inst { +} pld_inst; + +typedef struct _sxtb_inst { + unsigned int Rd; + unsigned int Rm; + unsigned int rotate; +} sxtb_inst; + +typedef struct _sxtab_inst { + unsigned int Rd; + unsigned int Rn; + unsigned int Rm; + unsigned rotate; +} sxtab_inst; + +typedef struct _sxtah_inst { + unsigned int Rd; + unsigned int Rn; + unsigned int Rm; + unsigned int rotate; +} sxtah_inst; + +typedef struct _sxth_inst { + unsigned int Rd; + unsigned int Rm; + unsigned int rotate; +} sxth_inst; + +typedef struct _uxtab_inst { + unsigned int Rn; + unsigned int Rd; + unsigned int rotate; + unsigned int Rm; +} uxtab_inst; + +typedef struct _uxtah_inst { + unsigned int Rn; + unsigned int Rd; + unsigned int rotate; + unsigned int Rm; +} uxtah_inst; + +typedef struct _uxth_inst { + unsigned int Rd; + unsigned int Rm; + unsigned int rotate; +} uxth_inst; + +typedef struct _cdp_inst { + unsigned int opcode_1; + unsigned int CRn; + unsigned int CRd; + unsigned int cp_num; + unsigned int opcode_2; + unsigned int CRm; + unsigned int inst; +}cdp_inst; + +typedef struct _uxtb_inst { + unsigned int Rd; + unsigned int Rm; + unsigned int rotate; +} uxtb_inst; + +typedef struct _swp_inst { + unsigned int Rn; + unsigned int Rd; + unsigned int Rm; +} swp_inst; + +typedef struct setend_inst { + unsigned int set_bigend; +} setend_inst; + +typedef struct _b_2_thumb { + unsigned int imm; +}b_2_thumb; +typedef struct _b_cond_thumb { + unsigned int imm; + unsigned int cond; +}b_cond_thumb; + +typedef struct _bl_1_thumb { + unsigned int imm; +}bl_1_thumb; +typedef struct _bl_2_thumb { + unsigned int imm; +}bl_2_thumb; +typedef struct _blx_1_thumb { + unsigned int imm; + unsigned int instr; +}blx_1_thumb; + +typedef struct _pkh_inst { + unsigned int Rm; + unsigned int Rn; + unsigned int Rd; + unsigned char imm; +} pkh_inst; + +typedef arm_inst * ARM_INST_PTR; + +inline void *AllocBuffer(ARMul_State* cpu,unsigned int size) { + int start = cpu->inst_bufftop; + cpu->inst_bufftop += size; + if (cpu->inst_bufftop > cpu->inst_buffsize) { + XDSERROR("inst_buf is full"); + CITRA_IGNORE_EXIT(-1); + } + return (void *)&cpu->inst_buf[start]; +} + +int CondPassed(ARMul_State* cpu, unsigned int cond) { + #define NFLAG cpu->NFlag + #define ZFLAG cpu->ZFlag + #define CFLAG cpu->CFlag + #define VFLAG cpu->VFlag + + int temp; + + switch (cond) { + case 0x0: + temp = ZFLAG; + break; + case 0x1: // NE + temp = !ZFLAG; + break; + case 0x6: // VS + temp = VFLAG; + break; + case 0x7: // VC + temp = !VFLAG; + break; + case 0x4: // MI + temp = NFLAG; + break; + case 0x5: // PL + temp = !NFLAG; + break; + case 0x2: // CS + temp = CFLAG; + break; + case 0x3: // CC + temp = !CFLAG; + break; + case 0x8: // HI + temp = (CFLAG && !ZFLAG); + break; + case 0x9: // LS + temp = (!CFLAG || ZFLAG); + break; + case 0xa: // GE + temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); + break; + case 0xb: // LT + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); + break; + case 0xc: // GT + temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)); + break; + case 0xd: // LE + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; + break; + case 0xe: // AL + temp = 1; + break; + case 0xf: + temp = 1; + break; + } + return temp; +} + +enum DECODE_STATUS { + DECODE_SUCCESS, + DECODE_FAILURE +}; + +int decode_arm_instr(uint32_t instr, int32_t *idx); + +static shtop_fp_t get_shtop(unsigned int inst) { + if (BIT(inst, 25)) { + return DPO(Immediate); + } else if (BITS(inst, 4, 11) == 0) { + return DPO(Register); + } else if (BITS(inst, 4, 6) == 0) { + return DPO(LogicalShiftLeftByImmediate); + } else if (BITS(inst, 4, 7) == 1) { + return DPO(LogicalShiftLeftByRegister); + } else if (BITS(inst, 4, 6) == 2) { + return DPO(LogicalShiftRightByImmediate); + } else if (BITS(inst, 4, 7) == 3) { + return DPO(LogicalShiftRightByRegister); + } else if (BITS(inst, 4, 6) == 4) { + return DPO(ArithmeticShiftRightByImmediate); + } else if (BITS(inst, 4, 7) == 5) { + return DPO(ArithmeticShiftRightByRegister); + } else if (BITS(inst, 4, 6) == 6) { + return DPO(RotateRightByImmediate); + } else if (BITS(inst, 4, 7) == 7) { + return DPO(RotateRightByRegister); + } + return nullptr; +} + +static get_addr_fp_t get_calc_addr_op(unsigned int inst) { + if (BITS(inst, 24, 27) == 5 && BIT(inst, 21) == 0) { + return LnSWoUB(ImmediateOffset); + } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 0 && BITS(inst, 4, 11) == 0) { + return LnSWoUB(RegisterOffset); + } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) { + return LnSWoUB(ScaledRegisterOffset); + } else if (BITS(inst, 24, 27) == 5 && BIT(inst, 21) == 1) { + return LnSWoUB(ImmediatePreIndexed); + } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 1 && BITS(inst, 4, 11) == 0) { + return LnSWoUB(RegisterPreIndexed); + } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 1 && BIT(inst, 4) == 0) { + return LnSWoUB(ScaledRegisterPreIndexed); + } else if (BITS(inst, 24, 27) == 4 && BIT(inst, 21) == 0) { + return LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BITS(inst, 4, 11) == 0) { + return LnSWoUB(RegisterPostIndexed); + } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) { + return LnSWoUB(ScaledRegisterPostIndexed); + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(ImmediateOffset); + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(RegisterOffset); + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(ImmediatePreIndexed); + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(RegisterPreIndexed); + } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(ImmediatePostIndexed); + } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + return MLnS(RegisterPostIndexed); + } else if (BITS(inst, 23, 27) == 0x11) { + return LdnStM(IncrementAfter); + } else if (BITS(inst, 23, 27) == 0x13) { + return LdnStM(IncrementBefore); + } else if (BITS(inst, 23, 27) == 0x10) { + return LdnStM(DecrementAfter); + } else if (BITS(inst, 23, 27) == 0x12) { + return LdnStM(DecrementBefore); + } + return nullptr; +} + +#define INTERPRETER_TRANSLATE(s) glue(InterpreterTranslate_, s) + +#define CHECK_RN (inst_cream->Rn == 15) +#define CHECK_RM (inst_cream->Rm == 15) +#define CHECK_RS (inst_cream->Rs == 15) + +#define UNIMPLEMENTED_INSTRUCTION(mnemonic) \ + XDSERROR("unimplemented instruction: %s", mnemonic); \ + CITRA_IGNORE_EXIT(-1); \ + return nullptr; + +static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(adc_inst)); + adc_inst *inst_cream = (adc_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(add_inst)); + add_inst *inst_cream = (add_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(and_inst)); + and_inst *inst_cream = (and_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) + inst_base->br = INDIRECT_BRANCH; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(ARMul_State* cpu,unsigned int inst, int index) +{ + #define POSBRANCH ((inst & 0x7fffff) << 2) + #define NEGBRANCH ((0xff000000 |(inst & 0xffffff)) << 2) + + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bbl_inst)); + bbl_inst *inst_cream = (bbl_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; + + if (BIT(inst, 24)) + inst_base->br = CALL; + if (BITS(inst, 28, 31) <= 0xe) + inst_base->br |= COND; + + inst_cream->L = BIT(inst, 24); + inst_cream->signed_immed_24 = BIT(inst, 23) ? NEGBRANCH : POSBRANCH; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bic_inst)); + bic_inst *inst_cream = (bic_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (inst_cream->Rd == 15) + inst_base->br = INDIRECT_BRANCH; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bkpt_inst)); + bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->imm = BITS(inst, 8, 19) | BITS(inst, 0, 3); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(blx_inst)); + blx_inst *inst_cream = (blx_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = INDIRECT_BRANCH; + + inst_cream->inst = inst; + if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { + inst_cream->val.Rm = BITS(inst, 0, 3); + } else { + inst_cream->val.signed_immed_24 = BITS(inst, 0, 23); + } + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bx_inst)); + bx_inst *inst_cream = (bx_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = INDIRECT_BRANCH; + + inst_cream->Rm = BITS(inst, 0, 3); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(bx)(cpu,inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(ARMul_State* cpu,unsigned int inst, int index) { + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(cdp_inst)); + cdp_inst *inst_cream = (cdp_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->CRm = BITS(inst, 0, 3); + inst_cream->CRd = BITS(inst, 12, 15); + inst_cream->CRn = BITS(inst, 16, 19); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->opcode_1 = BITS(inst, 20, 23); + inst_cream->inst = inst; + + LOG("inst %x index %x", inst, index); + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(clrex_inst)); + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(clz_inst)); + clz_inst *inst_cream = (clz_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RM) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(cmn_inst)); + cmn_inst *inst_cream = (cmn_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); + + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(cmp_inst)); + cmp_inst *inst_cream = (cmp_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(cps_inst)); + cps_inst *inst_cream = (cps_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->imod0 = BIT(inst, 18); + inst_cream->imod1 = BIT(inst, 19); + inst_cream->mmod = BIT(inst, 17); + inst_cream->A = BIT(inst, 8); + inst_cream->I = BIT(inst, 7); + inst_cream->F = BIT(inst, 6); + inst_cream->mode = BITS(inst, 0, 4); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mov_inst)); + mov_inst *inst_cream = (mov_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(eor_inst)); + eor_inst *inst_cream = (eor_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + if (CHECK_RN) + inst_base->load_r15 = 1; + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldc_inst)); + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BIT(inst, 15)) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sxtb_inst)); + sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->rotate = BITS(inst, 10, 11); + if (CHECK_RM) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(uxth_inst)); + uxth_inst *inst_cream = (uxth_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + if (CHECK_RM) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(uxtah_inst)); + uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + if (CHECK_RM || CHECK_RN) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + if (BITS(inst, 25, 27) == 2) { + inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); + } else { + DEBUG_MSG; + } + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = (BITS(inst, 12, 15) == 15) ? INDIRECT_BRANCH : NON_BRANCH; // Branch if dest is R15 + + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ldrex)(cpu,inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ldrex)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ldrex)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + if (BITS(inst, 25, 27) == 2) { + inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); + } else { + // Reaching this would indicate the thumb version + // of this instruction, however the 3DS CPU doesn't + // support this variant (the 3DS CPU is only ARMv6K, + // while this variant is added in ARMv6T2). + // So it's sufficient for citra to not implement this. + DEBUG_MSG; + } + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mcr_inst)); + mcr_inst *inst_cream = (mcr_inst *)inst_base->component; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->crn = BITS(inst, 16, 19); + inst_cream->crm = BITS(inst, 0, 3); + inst_cream->opcode_1 = BITS(inst, 21, 23); + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->inst = inst; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(ARMul_State* cpu,unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MCRR"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mla_inst)); + mla_inst *inst_cream = (mla_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rm = BITS(inst, 0, 3); + + if (CHECK_RM || CHECK_RN || CHECK_RS) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mov_inst)); + mov_inst *inst_cream = (mov_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mrc_inst)); + mrc_inst *inst_cream = (mrc_inst *)inst_base->component; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->crn = BITS(inst, 16, 19); + inst_cream->crm = BITS(inst, 0, 3); + inst_cream->opcode_1 = BITS(inst, 21, 23); + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->inst = inst; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(ARMul_State* cpu,unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MRRC"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mrs_inst)); + mrs_inst *inst_cream = (mrs_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->R = BIT(inst, 22); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(msr_inst)); + msr_inst *inst_cream = (msr_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->field_mask = BITS(inst, 16, 19); + inst_cream->R = BIT(inst, 22); + inst_cream->inst = inst; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mul_inst)); + mul_inst *inst_cream = (mul_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(mvn_inst)); + mvn_inst *inst_cream = (mvn_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; + +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(orr_inst)); + orr_inst *inst_cream = (orr_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (CHECK_RN) + inst_base->load_r15 = 1; + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(pkh_inst)); + pkh_inst *inst_cream = (pkh_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->imm = BITS(inst, 7, 11); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(pkhbt)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(pld_inst)); + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->op1 = BITS(inst, 21, 22); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(qadd8)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(rev_inst)); + rev_inst* const inst_cream = (rev_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(rev)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(rev)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = AL; + inst_base->idx = index; + inst_base->br = INDIRECT_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(rsb_inst)); + rsb_inst *inst_cream = (rsb_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (CHECK_RN) + inst_base->load_r15 = 1; + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(rsc_inst)); + rsc_inst *inst_cream = (rsc_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (CHECK_RN) + inst_base->load_r15 = 1; + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sadd8)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sbc_inst)); + sbc_inst *inst_cream = (sbc_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (CHECK_RN) + inst_base->load_r15 = 1; + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(setend_inst)); + setend_inst* const inst_cream = (setend_inst*)inst_base->component; + + inst_base->cond = AL; + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->set_bigend = BIT(inst, 9); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(shadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(shadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(shadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(shadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(shadd8)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smla_inst)); + smla_inst *inst_cream = (smla_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rn = BITS(inst, 12, 15); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->m = BIT(inst, 5); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(umlal_inst)); + umlal_inst *inst_cream = (umlal_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->RdLo = BITS(inst, 12, 15); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlalxy_inst)); + smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); + inst_cream->RdLo = BITS(inst, 12, 15); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->Rn = BITS(inst, 0, 4); + inst_cream->Rm = BITS(inst, 8, 11); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->m = BIT(inst, 6); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlald_inst)); + smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->RdLo = BITS(inst, 12, 15); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->swap = BIT(inst, 5); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlald)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->m = BIT(inst, 5); + inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smmla)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smmla)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smul_inst)); + smul_inst *inst_cream = (smul_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rm = BITS(inst, 0, 3); + + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + return inst_base; + +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(umull_inst)); + umull_inst *inst_cream = (umull_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->RdLo = BITS(inst, 12, 15); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst *inst_cream = (smlad_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->m = BIT(inst, 6); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 16, 19); + + if (CHECK_RM || CHECK_RN) + inst_base->load_r15 = 1; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = AL; + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ssat_inst)); + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->imm5 = BITS(inst, 7, 11); + inst_cream->sat_imm = BITS(inst, 16, 20); + inst_cream->shift_type = BIT(inst, 6); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ssat_inst)); + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->sat_imm = BITS(inst, 16, 19); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(stc_inst)); + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sxtb_inst)); + sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->rotate = BITS(inst, 10, 11); + + if (CHECK_RM) + inst_base->load_r15 = 1; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(uxth_inst)); + uxth_inst *inst_cream = (uxth_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + + if (CHECK_RM) + inst_base->load_r15 = 1; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(uxtab_inst)); + uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + + if (BITS(inst, 25, 27) == 2) { + inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); + } else { + DEBUG_MSG; + } + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(ARMul_State* cpu,unsigned int inst, int index){ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(strex)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(strex)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(strex)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->inst = inst; + if (BITS(inst, 25, 27) == 2) { + inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); + } else { + // Reaching this would indicate the thumb version + // of this instruction, however the 3DS CPU doesn't + // support this variant (the 3DS CPU is only ARMv6K, + // while this variant is added in ARMv6T2). + // So it's sufficient for citra to not implement this. + DEBUG_MSG; + } + + if (BITS(inst, 12, 15) == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sub_inst)); + sub_inst *inst_cream = (sub_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + if (CHECK_RN) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(swi_inst)); + swi_inst *inst_cream = (swi_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->num = BITS(inst, 0, 23); + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(swp_inst)); + swp_inst *inst_cream = (swp_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(ARMul_State* cpu,unsigned int inst, int index){ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(swp_inst)); + swp_inst *inst_cream = (swp_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(ARMul_State* cpu,unsigned int inst, int index){ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sxtab_inst)); + sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sxtab_inst)); + sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(sxtab16)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(ARMul_State* cpu,unsigned int inst, int index) { + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(sxtah_inst)); + sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(teq_inst)); + teq_inst *inst_cream = (teq_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + + if (CHECK_RN) + inst_base->load_r15 = 1; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(tst_inst)); + tst_inst *inst_cream = (tst_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->shifter_operand = BITS(inst, 0, 11); + inst_cream->shtop_func = get_shtop(inst); + if (inst_cream->Rd == 15) { + inst_base->br = INDIRECT_BRANCH; + } + + if (CHECK_RN) + inst_base->load_r15 = 1; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uadd8)(cpu, inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uhadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uhadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uhadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uhadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uhadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(umaal_inst)); + umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->RdLo = BITS(inst, 12, 15); + inst_cream->RdHi = BITS(inst, 16, 19); + + if (CHECK_RM || CHECK_RN) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(umlal_inst)); + umlal_inst *inst_cream = (umlal_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->RdLo = BITS(inst, 12, 15); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(umull_inst)); + umull_inst *inst_cream = (umull_inst *)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->RdHi = BITS(inst, 16, 19); + inst_cream->RdLo = BITS(inst, 12, 15); + + if (CHECK_RM || CHECK_RS) + inst_base->load_r15 = 1; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(ARMul_State* cpu,unsigned int tinst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(b_2_thumb)); + b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component; + + inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0); + + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(ARMul_State* cpu,unsigned int tinst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(b_cond_thumb)); + b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component; + + inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); + inst_cream->cond = ((tinst >> 8) & 0xf); + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(ARMul_State* cpu,unsigned int tinst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bl_1_thumb)); + bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component; + + inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0)); + + inst_base->idx = index; + inst_base->br = NON_BRANCH; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(ARMul_State* cpu,unsigned int tinst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(bl_2_thumb)); + bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component; + + inst_cream->imm = (tinst & 0x07FF) << 1; + + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(ARMul_State* cpu,unsigned int tinst, int index) +{ + arm_inst *inst_base = (arm_inst *)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(blx_1_thumb)); + blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component; + + inst_cream->imm = (tinst & 0x07FF) << 1; + inst_cream->instr = tinst; + + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 21); + inst_cream->op2 = BITS(inst, 5, 7); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uqadd8)(cpu,inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uqadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uqadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uqadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uqadd8)(cpu, inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->op1 = BITS(inst, 20, 24); + inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Ra = BITS(inst, 12, 15); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(usada8)(cpu,inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ssat)(cpu,inst, index); +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ssat16)(cpu,inst, index); +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(ARMul_State* cpu,unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(cpu,sizeof(arm_inst) + sizeof(uxtab_inst)); + uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->rotate = BITS(inst, 10, 11); + + return inst_base; +} +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(ARMul_State* cpu,unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(uxtab16)(cpu,inst, index); +} + +// Floating point VFPv3 structures and instructions + +#define VFP_INTERPRETER_STRUCT +#include "arm/skyeye_common/vfp/vfpinstr.cpp" +#undef VFP_INTERPRETER_STRUCT + +#define VFP_INTERPRETER_TRANS +#include "arm/skyeye_common/vfp/vfpinstr.cpp" +#undef VFP_INTERPRETER_TRANS + +typedef ARM_INST_PTR(*transop_fp_t)(ARMul_State* cpu,unsigned int, int); + +const transop_fp_t arm_instruction_trans[] = { + INTERPRETER_TRANSLATE(vmla), + INTERPRETER_TRANSLATE(vmls), + INTERPRETER_TRANSLATE(vnmla), + INTERPRETER_TRANSLATE(vnmla), + INTERPRETER_TRANSLATE(vnmls), + INTERPRETER_TRANSLATE(vnmul), + INTERPRETER_TRANSLATE(vmul), + INTERPRETER_TRANSLATE(vadd), + INTERPRETER_TRANSLATE(vsub), + INTERPRETER_TRANSLATE(vdiv), + INTERPRETER_TRANSLATE(vmovi), + INTERPRETER_TRANSLATE(vmovr), + INTERPRETER_TRANSLATE(vabs), + INTERPRETER_TRANSLATE(vneg), + INTERPRETER_TRANSLATE(vsqrt), + INTERPRETER_TRANSLATE(vcmp), + INTERPRETER_TRANSLATE(vcmp2), + INTERPRETER_TRANSLATE(vcvtbds), + INTERPRETER_TRANSLATE(vcvtbff), + INTERPRETER_TRANSLATE(vcvtbfi), + INTERPRETER_TRANSLATE(vmovbrs), + INTERPRETER_TRANSLATE(vmsr), + INTERPRETER_TRANSLATE(vmovbrc), + INTERPRETER_TRANSLATE(vmrs), + INTERPRETER_TRANSLATE(vmovbcr), + INTERPRETER_TRANSLATE(vmovbrrss), + INTERPRETER_TRANSLATE(vmovbrrd), + INTERPRETER_TRANSLATE(vstr), + INTERPRETER_TRANSLATE(vpush), + INTERPRETER_TRANSLATE(vstm), + INTERPRETER_TRANSLATE(vpop), + INTERPRETER_TRANSLATE(vldr), + INTERPRETER_TRANSLATE(vldm), + + INTERPRETER_TRANSLATE(srs), + INTERPRETER_TRANSLATE(rfe), + INTERPRETER_TRANSLATE(bkpt), + INTERPRETER_TRANSLATE(blx), + INTERPRETER_TRANSLATE(cps), + INTERPRETER_TRANSLATE(pld), + INTERPRETER_TRANSLATE(setend), + INTERPRETER_TRANSLATE(clrex), + INTERPRETER_TRANSLATE(rev16), + INTERPRETER_TRANSLATE(usad8), + INTERPRETER_TRANSLATE(sxtb), + INTERPRETER_TRANSLATE(uxtb), + INTERPRETER_TRANSLATE(sxth), + INTERPRETER_TRANSLATE(sxtb16), + INTERPRETER_TRANSLATE(uxth), + INTERPRETER_TRANSLATE(uxtb16), + INTERPRETER_TRANSLATE(cpy), + INTERPRETER_TRANSLATE(uxtab), + INTERPRETER_TRANSLATE(ssub8), + INTERPRETER_TRANSLATE(shsub8), + INTERPRETER_TRANSLATE(ssubaddx), + INTERPRETER_TRANSLATE(strex), + INTERPRETER_TRANSLATE(strexb), + INTERPRETER_TRANSLATE(swp), + INTERPRETER_TRANSLATE(swpb), + INTERPRETER_TRANSLATE(ssub16), + INTERPRETER_TRANSLATE(ssat16), + INTERPRETER_TRANSLATE(shsubaddx), + INTERPRETER_TRANSLATE(qsubaddx), + INTERPRETER_TRANSLATE(shaddsubx), + INTERPRETER_TRANSLATE(shadd8), + INTERPRETER_TRANSLATE(shadd16), + INTERPRETER_TRANSLATE(sel), + INTERPRETER_TRANSLATE(saddsubx), + INTERPRETER_TRANSLATE(sadd8), + INTERPRETER_TRANSLATE(sadd16), + INTERPRETER_TRANSLATE(shsub16), + INTERPRETER_TRANSLATE(umaal), + INTERPRETER_TRANSLATE(uxtab16), + INTERPRETER_TRANSLATE(usubaddx), + INTERPRETER_TRANSLATE(usub8), + INTERPRETER_TRANSLATE(usub16), + INTERPRETER_TRANSLATE(usat16), + INTERPRETER_TRANSLATE(usada8), + INTERPRETER_TRANSLATE(uqsubaddx), + INTERPRETER_TRANSLATE(uqsub8), + INTERPRETER_TRANSLATE(uqsub16), + INTERPRETER_TRANSLATE(uqaddsubx), + INTERPRETER_TRANSLATE(uqadd8), + INTERPRETER_TRANSLATE(uqadd16), + INTERPRETER_TRANSLATE(sxtab), + INTERPRETER_TRANSLATE(uhsubaddx), + INTERPRETER_TRANSLATE(uhsub8), + INTERPRETER_TRANSLATE(uhsub16), + INTERPRETER_TRANSLATE(uhaddsubx), + INTERPRETER_TRANSLATE(uhadd8), + INTERPRETER_TRANSLATE(uhadd16), + INTERPRETER_TRANSLATE(uaddsubx), + INTERPRETER_TRANSLATE(uadd8), + INTERPRETER_TRANSLATE(uadd16), + INTERPRETER_TRANSLATE(sxtah), + INTERPRETER_TRANSLATE(sxtab16), + INTERPRETER_TRANSLATE(qadd8), + INTERPRETER_TRANSLATE(bxj), + INTERPRETER_TRANSLATE(clz), + INTERPRETER_TRANSLATE(uxtah), + INTERPRETER_TRANSLATE(bx), + INTERPRETER_TRANSLATE(rev), + INTERPRETER_TRANSLATE(blx), + INTERPRETER_TRANSLATE(revsh), + INTERPRETER_TRANSLATE(qadd), + INTERPRETER_TRANSLATE(qadd16), + INTERPRETER_TRANSLATE(qaddsubx), + INTERPRETER_TRANSLATE(ldrex), + INTERPRETER_TRANSLATE(qdadd), + INTERPRETER_TRANSLATE(qdsub), + INTERPRETER_TRANSLATE(qsub), + INTERPRETER_TRANSLATE(ldrexb), + INTERPRETER_TRANSLATE(qsub8), + INTERPRETER_TRANSLATE(qsub16), + INTERPRETER_TRANSLATE(smuad), + INTERPRETER_TRANSLATE(smmul), + INTERPRETER_TRANSLATE(smusd), + INTERPRETER_TRANSLATE(smlsd), + INTERPRETER_TRANSLATE(smlsld), + INTERPRETER_TRANSLATE(smmla), + INTERPRETER_TRANSLATE(smmls), + INTERPRETER_TRANSLATE(smlald), + INTERPRETER_TRANSLATE(smlad), + INTERPRETER_TRANSLATE(smlaw), + INTERPRETER_TRANSLATE(smulw), + INTERPRETER_TRANSLATE(pkhtb), + INTERPRETER_TRANSLATE(pkhbt), + INTERPRETER_TRANSLATE(smul), + INTERPRETER_TRANSLATE(smlalxy), + INTERPRETER_TRANSLATE(smla), + INTERPRETER_TRANSLATE(mcrr), + INTERPRETER_TRANSLATE(mrrc), + INTERPRETER_TRANSLATE(cmp), + INTERPRETER_TRANSLATE(tst), + INTERPRETER_TRANSLATE(teq), + INTERPRETER_TRANSLATE(cmn), + INTERPRETER_TRANSLATE(smull), + INTERPRETER_TRANSLATE(umull), + INTERPRETER_TRANSLATE(umlal), + INTERPRETER_TRANSLATE(smlal), + INTERPRETER_TRANSLATE(mul), + INTERPRETER_TRANSLATE(mla), + INTERPRETER_TRANSLATE(ssat), + INTERPRETER_TRANSLATE(usat), + INTERPRETER_TRANSLATE(mrs), + INTERPRETER_TRANSLATE(msr), + INTERPRETER_TRANSLATE(and), + INTERPRETER_TRANSLATE(bic), + INTERPRETER_TRANSLATE(ldm), + INTERPRETER_TRANSLATE(eor), + INTERPRETER_TRANSLATE(add), + INTERPRETER_TRANSLATE(rsb), + INTERPRETER_TRANSLATE(rsc), + INTERPRETER_TRANSLATE(sbc), + INTERPRETER_TRANSLATE(adc), + INTERPRETER_TRANSLATE(sub), + INTERPRETER_TRANSLATE(orr), + INTERPRETER_TRANSLATE(mvn), + INTERPRETER_TRANSLATE(mov), + INTERPRETER_TRANSLATE(stm), + INTERPRETER_TRANSLATE(ldm), + INTERPRETER_TRANSLATE(ldrsh), + INTERPRETER_TRANSLATE(stm), + INTERPRETER_TRANSLATE(ldm), + INTERPRETER_TRANSLATE(ldrsb), + INTERPRETER_TRANSLATE(strd), + INTERPRETER_TRANSLATE(ldrh), + INTERPRETER_TRANSLATE(strh), + INTERPRETER_TRANSLATE(ldrd), + INTERPRETER_TRANSLATE(strt), + INTERPRETER_TRANSLATE(strbt), + INTERPRETER_TRANSLATE(ldrbt), + INTERPRETER_TRANSLATE(ldrt), + INTERPRETER_TRANSLATE(mrc), + INTERPRETER_TRANSLATE(mcr), + INTERPRETER_TRANSLATE(msr), + INTERPRETER_TRANSLATE(ldrb), + INTERPRETER_TRANSLATE(strb), + INTERPRETER_TRANSLATE(ldr), + INTERPRETER_TRANSLATE(ldrcond), + INTERPRETER_TRANSLATE(str), + INTERPRETER_TRANSLATE(cdp), + INTERPRETER_TRANSLATE(stc), + INTERPRETER_TRANSLATE(ldc), + INTERPRETER_TRANSLATE(swi), + INTERPRETER_TRANSLATE(bbl), + INTERPRETER_TRANSLATE(ldrexd), + INTERPRETER_TRANSLATE(strexd), + INTERPRETER_TRANSLATE(ldrexh), + INTERPRETER_TRANSLATE(strexh), + + // All the thumb instructions should be placed the end of table + INTERPRETER_TRANSLATE(b_2_thumb), + INTERPRETER_TRANSLATE(b_cond_thumb), + INTERPRETER_TRANSLATE(bl_1_thumb), + INTERPRETER_TRANSLATE(bl_2_thumb), + INTERPRETER_TRANSLATE(blx_1_thumb) +}; + +static void insert_bb(ARMul_State * cpu,unsigned int addr, int start) { + (*(cpu->CreamCache))[addr] = start; +} + +static int find_bb(ARMul_State * cpu, unsigned int addr, int& start) { + int ret = -1; + bb_map::const_iterator it = cpu->CreamCache->find(addr); + if (it != cpu->CreamCache->end()) { + start = static_cast(it->second); + ret = 0; + } else { + ret = -1; + } + return ret; +} + +enum { + FETCH_SUCCESS, + FETCH_FAILURE +}; + +static tdstate decode_thumb_instr(ARMul_State* cpu, uint32_t inst, addr_t addr, uint32_t* arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){ + // Check if in Thumb mode + tdstate ret = thumb_translate (addr, inst, arm_inst, inst_size); + if(ret == t_branch){ + // TODO: FIXME, endian should be judged + u32 tinstr; + if((addr & 0x3) != 0) + tinstr = inst >> 16; + else + tinstr = inst & 0xFFFF; + + int inst_index; + int table_length = sizeof(arm_instruction_trans) / sizeof(transop_fp_t); + + switch((tinstr & 0xF800) >> 11){ + case 26: + case 27: + if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){ + inst_index = table_length - 4; + *ptr_inst_base = arm_instruction_trans[inst_index](cpu,tinstr, inst_index); + } else { + XDSERROR("thumb decoder error"); + } + break; + case 28: + // Branch 2, unconditional branch + inst_index = table_length - 5; + *ptr_inst_base = arm_instruction_trans[inst_index](cpu,tinstr, inst_index); + break; + + case 8: + case 29: + // For BLX 1 thumb instruction + inst_index = table_length - 1; + *ptr_inst_base = arm_instruction_trans[inst_index](cpu,tinstr, inst_index); + break; + case 30: + // For BL 1 thumb instruction + inst_index = table_length - 3; + *ptr_inst_base = arm_instruction_trans[inst_index](cpu,tinstr, inst_index); + break; + case 31: + // For BL 2 thumb instruction + inst_index = table_length - 2; + *ptr_inst_base = arm_instruction_trans[inst_index](cpu,tinstr, inst_index); + break; + default: + ret = t_undefined; + break; + } + } + return ret; +} + +enum { + KEEP_GOING, + FETCH_EXCEPTION +}; + +typedef struct instruction_set_encoding_item ISEITEM; + +extern const ISEITEM arm_instruction[]; + +static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, addr_t addr) { + + // Decode instruction, get index + // Allocate memory and init InsCream + // Go on next, until terminal instruction + // Save start addr of basicblock in CreamCache + ARM_INST_PTR inst_base = nullptr; + unsigned int inst, inst_size = 4; + int idx; + int ret = NON_BRANCH; + int thumb = 0; + int size = 0; // instruction size of basic block + bb_start = cpu->inst_bufftop; + + if (cpu->TFlag) + thumb = THUMB; + + addr_t phys_addr = addr; + addr_t pc_start = cpu->Reg[15]; + + while(ret == NON_BRANCH) { + inst = ARMul_LoadInstrS(cpu, phys_addr & 0xFFFFFFFC, 4); + + size++; + // If we are in thumb instruction, we will translate one thumb to one corresponding arm instruction + if (cpu->TFlag) { + uint32_t arm_inst; + tdstate state; + state = decode_thumb_instr(cpu, inst, phys_addr, &arm_inst, &inst_size, &inst_base); + + // We have translated the branch instruction of thumb in thumb decoder + if(state == t_branch){ + goto translated; + } + inst = arm_inst; + } + + ret = decode_arm_instr(inst, &idx); + if (ret == DECODE_FAILURE) { + std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); + XDSERROR("Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst); + XDSERROR("cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]); + CITRA_IGNORE_EXIT(-1); + } + inst_base = arm_instruction_trans[idx](cpu,inst, idx); +translated: + phys_addr += inst_size; + + if ((phys_addr & 0xfff) == 0) { + inst_base->br = END_OF_PAGE; + } + ret = inst_base->br; + }; + insert_bb(cpu,pc_start, bb_start); + return KEEP_GOING; +} + +static int clz(unsigned int x) { + int n; + if (x == 0) return (32); + n = 1; + if ((x >> 16) == 0) { n = n + 16; x = x << 16;} + if ((x >> 24) == 0) { n = n + 8; x = x << 8;} + if ((x >> 28) == 0) { n = n + 4; x = x << 4;} + if ((x >> 30) == 0) { n = n + 2; x = x << 2;} + n = n - (x >> 31); + return n; +} +#ifdef inst_debug +void inst_deb(ARMul_State* cpu) +{ + if (strcmp(LOGMODULE, cpu->m_currentThread->m_owner->GetName()) == 0) + { + if (cpu->Reg[15] >= 0x00100040) + { + for (int i = 0; i < 4; i++) + LOG("%08x %08x %08x %08x", cpu->Reg[0 + i * 4], cpu->Reg[1 + i * 4], cpu->Reg[2 + i * 4], cpu->Reg[3 + i * 4]); + LOG(""); + } + } +} +#endif +unsigned InterpreterMainLoop(ARMul_State* state) { + +#undef RM +#undef RS + +#define CRn inst_cream->crn +#define OPCODE_1 inst_cream->opcode_1 +#define OPCODE_2 inst_cream->opcode_2 +#define CRm inst_cream->crm +#define CP15_REG(n) cpu->CP15[CP15(n)] +#define RD cpu->Reg[inst_cream->Rd] +#define RD2 cpu->Reg[inst_cream->Rd + 1] +#define RN cpu->Reg[inst_cream->Rn] +#define RM cpu->Reg[inst_cream->Rm] +#define RS cpu->Reg[inst_cream->Rs] +#define RDHI cpu->Reg[inst_cream->RdHi] +#define RDLO cpu->Reg[inst_cream->RdLo] +#define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4) +#define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24) +#define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand) + +#ifdef inst_debug +#define FETCH_INST inst_deb(cpu); \ + if (inst_base->br != NON_BRANCH) goto DISPATCH; \ + inst_base = (arm_inst *)&cpu->inst_buf[ptr] +#else +#define FETCH_INST if (inst_base->br != NON_BRANCH) goto DISPATCH; \ + inst_base = (arm_inst *)&cpu->inst_buf[ptr] +#endif + + #define INC_PC(l) ptr += sizeof(arm_inst) + l + +// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a +// clunky switch statement. +#if defined __GNUC__ || defined __clang__ +#define GOTO_NEXT_INST \ + if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ + num_instrs++; \ + goto *InstLabel[inst_base->idx] +#else +#define GOTO_NEXT_INST \ + if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ + num_instrs++; \ + switch(inst_base->idx) { \ + case 0: goto VMLA_INST; \ + case 1: goto VMLS_INST; \ + case 2: goto VNMLA_INST; \ + case 3: goto VNMLA_INST; \ + case 4: goto VNMLS_INST; \ + case 5: goto VNMUL_INST; \ + case 6: goto VMUL_INST; \ + case 7: goto VADD_INST; \ + case 8: goto VSUB_INST; \ + case 9: goto VDIV_INST; \ + case 10: goto VMOVI_INST; \ + case 11: goto VMOVR_INST; \ + case 12: goto VABS_INST; \ + case 13: goto VNEG_INST; \ + case 14: goto VSQRT_INST; \ + case 15: goto VCMP_INST; \ + case 16: goto VCMP2_INST; \ + case 17: goto VCVTBDS_INST; \ + case 18: goto VCVTBFF_INST; \ + case 19: goto VCVTBFI_INST; \ + case 20: goto VMOVBRS_INST; \ + case 21: goto VMSR_INST; \ + case 22: goto VMOVBRC_INST; \ + case 23: goto VMRS_INST; \ + case 24: goto VMOVBCR_INST; \ + case 25: goto VMOVBRRSS_INST; \ + case 26: goto VMOVBRRD_INST; \ + case 27: goto VSTR_INST; \ + case 28: goto VPUSH_INST; \ + case 29: goto VSTM_INST; \ + case 30: goto VPOP_INST; \ + case 31: goto VLDR_INST; \ + case 32: goto VLDM_INST ; \ + case 33: goto SRS_INST; \ + case 34: goto RFE_INST; \ + case 35: goto BKPT_INST; \ + case 36: goto BLX_INST; \ + case 37: goto CPS_INST; \ + case 38: goto PLD_INST; \ + case 39: goto SETEND_INST; \ + case 40: goto CLREX_INST; \ + case 41: goto REV16_INST; \ + case 42: goto USAD8_INST; \ + case 43: goto SXTB_INST; \ + case 44: goto UXTB_INST; \ + case 45: goto SXTH_INST; \ + case 46: goto SXTB16_INST; \ + case 47: goto UXTH_INST; \ + case 48: goto UXTB16_INST; \ + case 49: goto CPY_INST; \ + case 50: goto UXTAB_INST; \ + case 51: goto SSUB8_INST; \ + case 52: goto SHSUB8_INST; \ + case 53: goto SSUBADDX_INST; \ + case 54: goto STREX_INST; \ + case 55: goto STREXB_INST; \ + case 56: goto SWP_INST; \ + case 57: goto SWPB_INST; \ + case 58: goto SSUB16_INST; \ + case 59: goto SSAT16_INST; \ + case 60: goto SHSUBADDX_INST; \ + case 61: goto QSUBADDX_INST; \ + case 62: goto SHADDSUBX_INST; \ + case 63: goto SHADD8_INST; \ + case 64: goto SHADD16_INST; \ + case 65: goto SEL_INST; \ + case 66: goto SADDSUBX_INST; \ + case 67: goto SADD8_INST; \ + case 68: goto SADD16_INST; \ + case 69: goto SHSUB16_INST; \ + case 70: goto UMAAL_INST; \ + case 71: goto UXTAB16_INST; \ + case 72: goto USUBADDX_INST; \ + case 73: goto USUB8_INST; \ + case 74: goto USUB16_INST; \ + case 75: goto USAT16_INST; \ + case 76: goto USADA8_INST; \ + case 77: goto UQSUBADDX_INST; \ + case 78: goto UQSUB8_INST; \ + case 79: goto UQSUB16_INST; \ + case 80: goto UQADDSUBX_INST; \ + case 81: goto UQADD8_INST; \ + case 82: goto UQADD16_INST; \ + case 83: goto SXTAB_INST; \ + case 84: goto UHSUBADDX_INST; \ + case 85: goto UHSUB8_INST; \ + case 86: goto UHSUB16_INST; \ + case 87: goto UHADDSUBX_INST; \ + case 88: goto UHADD8_INST; \ + case 89: goto UHADD16_INST; \ + case 90: goto UADDSUBX_INST; \ + case 91: goto UADD8_INST; \ + case 92: goto UADD16_INST; \ + case 93: goto SXTAH_INST; \ + case 94: goto SXTAB16_INST; \ + case 95: goto QADD8_INST; \ + case 96: goto BXJ_INST; \ + case 97: goto CLZ_INST; \ + case 98: goto UXTAH_INST; \ + case 99: goto BX_INST; \ + case 100: goto REV_INST; \ + case 101: goto BLX_INST; \ + case 102: goto REVSH_INST; \ + case 103: goto QADD_INST; \ + case 104: goto QADD16_INST; \ + case 105: goto QADDSUBX_INST; \ + case 106: goto LDREX_INST; \ + case 107: goto QDADD_INST; \ + case 108: goto QDSUB_INST; \ + case 109: goto QSUB_INST; \ + case 110: goto LDREXB_INST; \ + case 111: goto QSUB8_INST; \ + case 112: goto QSUB16_INST; \ + case 113: goto SMUAD_INST; \ + case 114: goto SMMUL_INST; \ + case 115: goto SMUSD_INST; \ + case 116: goto SMLSD_INST; \ + case 117: goto SMLSLD_INST; \ + case 118: goto SMMLA_INST; \ + case 119: goto SMMLS_INST; \ + case 120: goto SMLALD_INST; \ + case 121: goto SMLAD_INST; \ + case 122: goto SMLAW_INST; \ + case 123: goto SMULW_INST; \ + case 124: goto PKHTB_INST; \ + case 125: goto PKHBT_INST; \ + case 126: goto SMUL_INST; \ + case 127: goto SMLALXY_INST; \ + case 128: goto SMLA_INST; \ + case 129: goto MCRR_INST; \ + case 130: goto MRRC_INST; \ + case 131: goto CMP_INST; \ + case 132: goto TST_INST; \ + case 133: goto TEQ_INST; \ + case 134: goto CMN_INST; \ + case 135: goto SMULL_INST; \ + case 136: goto UMULL_INST; \ + case 137: goto UMLAL_INST; \ + case 138: goto SMLAL_INST; \ + case 139: goto MUL_INST; \ + case 140: goto MLA_INST; \ + case 141: goto SSAT_INST; \ + case 142: goto USAT_INST; \ + case 143: goto MRS_INST; \ + case 144: goto MSR_INST; \ + case 145: goto AND_INST; \ + case 146: goto BIC_INST; \ + case 147: goto LDM_INST; \ + case 148: goto EOR_INST; \ + case 149: goto ADD_INST; \ + case 150: goto RSB_INST; \ + case 151: goto RSC_INST; \ + case 152: goto SBC_INST; \ + case 153: goto ADC_INST; \ + case 154: goto SUB_INST; \ + case 155: goto ORR_INST; \ + case 156: goto MVN_INST; \ + case 157: goto MOV_INST; \ + case 158: goto STM_INST; \ + case 159: goto LDM_INST; \ + case 160: goto LDRSH_INST; \ + case 161: goto STM_INST; \ + case 162: goto LDM_INST; \ + case 163: goto LDRSB_INST; \ + case 164: goto STRD_INST; \ + case 165: goto LDRH_INST; \ + case 166: goto STRH_INST; \ + case 167: goto LDRD_INST; \ + case 168: goto STRT_INST; \ + case 169: goto STRBT_INST; \ + case 170: goto LDRBT_INST; \ + case 171: goto LDRT_INST; \ + case 172: goto MRC_INST; \ + case 173: goto MCR_INST; \ + case 174: goto MSR_INST; \ + case 175: goto LDRB_INST; \ + case 176: goto STRB_INST; \ + case 177: goto LDR_INST; \ + case 178: goto LDRCOND_INST ; \ + case 179: goto STR_INST; \ + case 180: goto CDP_INST; \ + case 181: goto STC_INST; \ + case 182: goto LDC_INST; \ + case 183: goto SWI_INST; \ + case 184: goto BBL_INST; \ + case 185: goto LDREXD_INST; \ + case 186: goto STREXD_INST; \ + case 187: goto LDREXH_INST; \ + case 188: goto STREXH_INST; \ + case 189: goto B_2_THUMB ; \ + case 190: goto B_COND_THUMB ; \ + case 191: goto BL_1_THUMB ; \ + case 192: goto BL_2_THUMB ; \ + case 193: goto BLX_1_THUMB ; \ + case 194: goto DISPATCH; \ + case 195: goto INIT_INST_LENGTH; \ + case 196: goto END; \ + } +#endif + + #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) + #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) + #define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) + + #define SAVE_NZCVT cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | \ + (cpu->NFlag << 31) | \ + (cpu->ZFlag << 30) | \ + (cpu->CFlag << 29) | \ + (cpu->VFlag << 28) | \ + (cpu->TFlag << 5) + #define LOAD_NZCVT cpu->NFlag = (cpu->Cpsr >> 31); \ + cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \ + cpu->CFlag = (cpu->Cpsr >> 29) & 1; \ + cpu->VFlag = (cpu->Cpsr >> 28) & 1; \ + cpu->TFlag = (cpu->Cpsr >> 5) & 1; + + #define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE) + #define PC (cpu->Reg[15]) + #define CHECK_EXT_INT if (!cpu->NirqSig && !(cpu->Cpsr & 0x80)) goto END; + + ARMul_State* cpu = state; + + // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback + // to a clunky switch statement. +#if defined __GNUC__ || defined __clang__ + void *InstLabel[] = { + &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST, + &&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST, + &&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST, + &&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST, + + &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST, + &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST, + &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST, + &&SHADD8_INST,&&SHADD16_INST,&&SEL_INST,&&SADDSUBX_INST,&&SADD8_INST,&&SADD16_INST,&&SHSUB16_INST,&&UMAAL_INST,&&UXTAB16_INST, + &&USUBADDX_INST,&&USUB8_INST,&&USUB16_INST,&&USAT16_INST,&&USADA8_INST,&&UQSUBADDX_INST,&&UQSUB8_INST,&&UQSUB16_INST, + &&UQADDSUBX_INST,&&UQADD8_INST,&&UQADD16_INST,&&SXTAB_INST,&&UHSUBADDX_INST,&&UHSUB8_INST,&&UHSUB16_INST,&&UHADDSUBX_INST,&&UHADD8_INST, + &&UHADD16_INST,&&UADDSUBX_INST,&&UADD8_INST,&&UADD16_INST,&&SXTAH_INST,&&SXTAB16_INST,&&QADD8_INST,&&BXJ_INST,&&CLZ_INST,&&UXTAH_INST, + &&BX_INST,&&REV_INST,&&BLX_INST,&&REVSH_INST,&&QADD_INST,&&QADD16_INST,&&QADDSUBX_INST,&&LDREX_INST,&&QDADD_INST,&&QDSUB_INST, + &&QSUB_INST,&&LDREXB_INST,&&QSUB8_INST,&&QSUB16_INST,&&SMUAD_INST,&&SMMUL_INST,&&SMUSD_INST,&&SMLSD_INST,&&SMLSLD_INST,&&SMMLA_INST, + &&SMMLS_INST,&&SMLALD_INST,&&SMLAD_INST,&&SMLAW_INST,&&SMULW_INST,&&PKHTB_INST,&&PKHBT_INST,&&SMUL_INST,&&SMLALXY_INST,&&SMLA_INST, + &&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST, + &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, + &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, + &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, + &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, + &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, + &&INIT_INST_LENGTH,&&END + }; +#endif + arm_inst* inst_base; + unsigned int addr; + unsigned int phys_addr; + unsigned int num_instrs = 0; + + int ptr; + + LOAD_NZCVT; + DISPATCH: + { +#ifdef inst_debug + inst_deb(cpu); +#endif + if (!cpu->NirqSig) { + if (!(cpu->Cpsr & 0x80)) { + goto END; + } + } + if (cpu->TFlag) + cpu->Reg[15] &= 0xfffffffe; + else + cpu->Reg[15] &= 0xfffffffc; + + phys_addr = cpu->Reg[15]; + + if (find_bb(cpu,cpu->Reg[15], ptr) == -1) + if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) + goto END; + + inst_base = (arm_inst *)&cpu->inst_buf[ptr]; + GOTO_NEXT_INST; + } + ADC_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + adc_inst* const inst_cream = (adc_inst*)inst_base->component; + + bool carry; + bool overflow; + RD = AddWithCarry(RN, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(adc_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(adc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + ADD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + add_inst* const inst_cream = (add_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + { + rn_val += 2 * GET_INST_SIZE(cpu); + rn_val &= ~0x3; + } + + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Cpsr & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(add_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(add_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + AND_INST: + { + and_inst *inst_cream = (and_inst *)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + RD = lop & rop; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Cpsr & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(and_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(and_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + BBL_INST: + { + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + bbl_inst *inst_cream = (bbl_inst *)inst_base->component; + if (inst_cream->L) { + LINK_RTN_ADDR; + } + SET_PC; + INC_PC(sizeof(bbl_inst)); + goto DISPATCH; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bbl_inst)); + goto DISPATCH; + } + BIC_INST: + { + bic_inst *inst_cream = (bic_inst *)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + u32 lop = RN; + if (inst_cream->Rn == 15) { + lop += 2 * GET_INST_SIZE(cpu); + } + u32 rop = SHIFTER_OPERAND; + RD = lop & (~rop); + if ((inst_cream->S) && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(bic_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bic_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + BKPT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; + LOG("Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bkpt_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + BLX_INST: + { + blx_inst *inst_cream = (blx_inst *)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + unsigned int inst = inst_cream->inst; + if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { + cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu)); + if(cpu->TFlag) + cpu->Reg[14] |= 0x1; + cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe; + cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1; + } else { + cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu)); + cpu->TFlag = 0x1; + int signed_int = inst_cream->val.signed_immed_24; + signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int; + signed_int = signed_int << 2; + cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1); + } + INC_PC(sizeof(blx_inst)); + goto DISPATCH; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(blx_inst)); + goto DISPATCH; + } + + BX_INST: + BXJ_INST: + { + // Note that only the 'fail' case of BXJ is emulated. This is because + // the facilities for Jazelle emulation are not implemented. + // + // According to the ARM documentation on BXJ, if setting the J bit in the APSR + // fails, then BXJ functions identically like a regular BX instruction. + // + // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle. + + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + bx_inst* const inst_cream = (bx_inst*)inst_base->component; + + if (inst_cream->Rm == 15) + LOG("BX at pc %x: use of Rm = R15 is discouraged", cpu->Reg[15]); + + cpu->TFlag = cpu->Reg[inst_cream->Rm] & 0x1; + cpu->Reg[15] = cpu->Reg[inst_cream->Rm] & 0xfffffffe; + INC_PC(sizeof(bx_inst)); + goto DISPATCH; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bx_inst)); + goto DISPATCH; + } + + CDP_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + // Undefined instruction here + cpu->NumInstrsToExecute = 0; + return num_instrs; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(cdp_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + CLREX_INST: + { + remove_exclusive(cpu, 0); + cpu->exclusive_state = 0; + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(clrex_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + CLZ_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + clz_inst* inst_cream = (clz_inst*)inst_base->component; + RD = clz(RM); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(clz_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + CMN_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + cmn_inst* const inst_cream = (cmn_inst*)inst_base->component; + + bool carry; + bool overflow; + u32 result = AddWithCarry(RN, SHIFTER_OPERAND, 0, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(cmn_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + CMP_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + cmp_inst* const inst_cream = (cmp_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * GET_INST_SIZE(cpu); + + bool carry; + bool overflow; + u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(cmp_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + CPS_INST: + { + cps_inst *inst_cream = (cps_inst *)inst_base->component; + uint32_t aif_val = 0; + uint32_t aif_mask = 0; + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(cps_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + CPY_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + + RD = SHIFTER_OPERAND; + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mov_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mov_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + EOR_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + eor_inst* inst_cream = (eor_inst*)inst_base->component; + + u32 lop = RN; + if (inst_cream->Rn == 15) { + lop += 2 * GET_INST_SIZE(cpu); + } + u32 rop = SHIFTER_OPERAND; + RD = lop ^ rop; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(eor_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(eor_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDC_INST: + { + // Instruction not implemented + //LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDM_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + unsigned int inst = inst_cream->inst; + if (BIT(inst, 22) && !BIT(inst, 15)) { + for (int i = 0; i < 13; i++) { + if(BIT(inst, i)) { + cpu->Reg[i] = ARMul_LoadWordN(cpu, addr); + addr += 4; + } + } + if (BIT(inst, 13)) { + if (cpu->Mode == USER32MODE) + cpu->Reg[13] = ARMul_LoadWordN(cpu, addr); + else + cpu->Reg_usr[0] = ARMul_LoadWordN(cpu, addr); + + addr += 4; + } + if (BIT(inst, 14)) { + if (cpu->Mode == USER32MODE) + cpu->Reg[14] = ARMul_LoadWordN(cpu, addr); + else + cpu->Reg_usr[1] = ARMul_LoadWordN(cpu, addr); + + addr += 4; + } + } else if (!BIT(inst, 22)) { + for(int i = 0; i < 16; i++ ){ + if(BIT(inst, i)){ + unsigned int ret = ARMul_LoadWordN(cpu, addr); + + // For armv5t, should enter thumb when bits[0] is non-zero. + if(i == 15){ + cpu->TFlag = ret & 0x1; + ret &= 0xFFFFFFFE; + } + + cpu->Reg[i] = ret; + addr += 4; + } + } + } else if (BIT(inst, 22) && BIT(inst, 15)) { + for(int i = 0; i < 15; i++ ){ + if(BIT(inst, i)){ + cpu->Reg[i] = ARMul_LoadWordN(cpu, addr); + addr += 4; + } + } + + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Cpsr & 0x1f); + LOAD_NZCVT; + } + + cpu->Reg[15] = ARMul_LoadWordN(cpu, addr); + } + + if (BIT(inst, 15)) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SXTH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxth_inst* inst_cream = (sxth_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); + if (BIT(operand2, 15)) { + operand2 |= 0xffff0000; + } else { + operand2 &= 0xffff; + } + RD = operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sxth_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDR_INST: + { + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + unsigned int value = ARMul_LoadWordN(cpu, addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + + if (BITS(inst_cream->inst, 12, 15) == 15) { + // For armv5t, should enter thumb when bits[0] is non-zero. + cpu->TFlag = value & 0x1; + cpu->Reg[15] &= 0xFFFFFFFE; + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRCOND_INST: + { + if (CondPassed(cpu, inst_base->cond)) { + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + unsigned int value = ARMul_LoadWordN(cpu, addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + + if (BITS(inst_cream->inst, 12, 15) == 15) { + // For armv5t, should enter thumb when bits[0] is non-zero. + cpu->TFlag = value & 0x1; + cpu->Reg[15] &= 0xFFFFFFFE; + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UXTH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxth_inst* inst_cream = (uxth_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxth_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UXTAH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + + RD = RN + operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxtah_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ARMul_LoadByte(cpu,addr); + + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRBT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ARMul_LoadByte(cpu,addr); + + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + // The 3DS doesn't have LPAE (Large Physical Access Extension), so it + // wouldn't do this as a single read. + cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = ARMul_LoadWordN(cpu, addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = ARMul_LoadWordN(cpu, addr + 4); + + // No dispatch since this operation should not modify R15 + } + cpu->Reg[15] += 4; + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + LDREX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; + + RD = ARMul_LoadWordN(cpu, read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDREXB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; + + RD = ARMul_LoadByte(cpu, read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDREXH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; + + RD = ARMul_LoadHalfWord(cpu, read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDREXD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; + + RD = ARMul_LoadWordN(cpu, read_addr); + RD2 = ARMul_LoadWordN(cpu, read_addr + 4); + + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ARMul_LoadHalfWord(cpu, addr); + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRSB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + unsigned int value = ARMul_LoadByte(cpu, addr); + if (BIT(value, 7)) { + value |= 0xffffff00; + } + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRSH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + unsigned int value = ARMul_LoadHalfWord(cpu, addr); + if (BIT(value, 15)) { + value |= 0xffff0000; + } + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDRT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + + unsigned int value = ARMul_LoadWordN(cpu, addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + + if (BITS(inst_cream->inst, 12, 15) == 15) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MCR_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mcr_inst* inst_cream = (mcr_inst*)inst_base->component; + + unsigned int inst = inst_cream->inst; + if (inst_cream->Rd == 15) { + DEBUG_MSG; + } else { + if (inst_cream->cp_num == 15) + WriteCP15Register(cpu, RD, CRn, OPCODE_1, CRm, OPCODE_2); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mcr_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MCRR_INST: + MLA_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mla_inst* inst_cream = (mla_inst*)inst_base->component; + + uint64_t rm = RM; + uint64_t rs = RS; + uint64_t rn = RN; + + RD = static_cast((rm * rs + rn) & 0xffffffff); + if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mla_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mla_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MOV_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + + RD = SHIFTER_OPERAND; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mov_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mov_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MRC_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mrc_inst* inst_cream = (mrc_inst*)inst_base->component; + + unsigned int inst = inst_cream->inst; + if (inst_cream->Rd == 15) { + DEBUG_MSG; + } + if (inst_cream->inst == 0xeef04a10) { + // Undefined instruction fmrx + RD = 0x20000000; + CITRA_IGNORE_EXIT(-1); + goto END; + } else { + if (inst_cream->cp_num == 15) + RD = ReadCP15Register(cpu, CRn, OPCODE_1, CRm, OPCODE_2); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mrc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MRRC_INST: + MRS_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mrs_inst* inst_cream = (mrs_inst*)inst_base->component; + + if (inst_cream->R) { + RD = cpu->Spsr_copy; + } else { + SAVE_NZCVT; + RD = cpu->Cpsr; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mrs_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MSR_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + msr_inst* inst_cream = (msr_inst*)inst_base->component; + const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; + unsigned int inst = inst_cream->inst; + unsigned int operand; + + if (BIT(inst, 25)) { + int rot_imm = BITS(inst, 8, 11) * 2; + operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm); + } else { + operand = cpu->Reg[BITS(inst, 0, 3)]; + } + uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) + | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0); + uint32_t mask = 0; + if (!inst_cream->R) { + mask = byte_mask & UserMask; + SAVE_NZCVT; + + cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); + switch_mode(cpu, cpu->Cpsr & 0x1f); + LOAD_NZCVT; + } else { + if (CurrentModeHasSPSR) { + mask = byte_mask & (UserMask | PrivMask | StateMask); + cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); + } + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(msr_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MUL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mul_inst* inst_cream = (mul_inst*)inst_base->component; + + uint64_t rm = RM; + uint64_t rs = RS; + RD = static_cast((rm * rs) & 0xffffffff); + if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mul_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mul_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + MVN_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mvn_inst* const inst_cream = (mvn_inst*)inst_base->component; + + RD = ~SHIFTER_OPERAND; + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mvn_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(mvn_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + ORR_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + orr_inst* const inst_cream = (orr_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + RD = lop | rop; + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(orr_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(orr_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + PKHBT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + pkh_inst *inst_cream = (pkh_inst *)inst_base->component; + RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(pkh_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + PKHTB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + pkh_inst *inst_cream = (pkh_inst *)inst_base->component; + int shift_imm = inst_cream->imm ? inst_cream->imm : 31; + RD = ((static_cast(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(pkh_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + PLD_INST: + { + // Not implemented. PLD is a hint instruction, so it's optional. + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(pld_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + QADD_INST: + QDADD_INST: + QDSUB_INST: + QSUB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u8 op1 = inst_cream->op1; + const u32 rm_val = RM; + const u32 rn_val = RN; + + u32 result = 0; + + // QADD + if (op1 == 0x00) { + result = rm_val + rn_val; + + if (AddOverflow(rm_val, rn_val, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + } + // QSUB + else if (op1 == 0x01) { + result = rm_val - rn_val; + + if (SubOverflow(rm_val, rn_val, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + } + // QDADD + else if (op1 == 0x02) { + u32 mul = (rn_val * 2); + + if (AddOverflow(rn_val, rn_val, rn_val * 2)) { + mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + + result = mul + rm_val; + + if (AddOverflow(rm_val, mul, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + } + // QDSUB + else if (op1 == 0x03) { + u32 mul = (rn_val * 2); + + if (AddOverflow(rn_val, rn_val, mul)) { + mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + + result = rm_val - mul; + + if (SubOverflow(rm_val, mul, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + } + + RD = result; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + QADD8_INST: + QADD16_INST: + QADDSUBX_INST: + QSUB8_INST: + QSUB16_INST: + QSUBADDX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u16 rm_lo = (RM & 0xFFFF); + const u16 rm_hi = ((RM >> 16) & 0xFFFF); + const u16 rn_lo = (RN & 0xFFFF); + const u16 rn_hi = ((RN >> 16) & 0xFFFF); + const u8 op2 = inst_cream->op2; + + u16 lo_result = 0; + u16 hi_result = 0; + + // QADD16 + if (op2 == 0x00) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi); + } + // QASX + else if (op2 == 0x01) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo); + } + // QSAX + else if (op2 == 0x02) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo); + } + // QSUB16 + else if (op2 == 0x03) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi); + } + // QADD8 + else if (op2 == 0x04) { + lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8; + } + // QSUB8 + else if (op2 == 0x07) { + lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8; + } + + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + REV_INST: + REV16_INST: + REVSH_INST: + { + + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + rev_inst* const inst_cream = (rev_inst*)inst_base->component; + + const u8 op1 = inst_cream->op1; + const u8 op2 = inst_cream->op2; + + // REV + if (op1 == 0x03 && op2 == 0x01) { + RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) | ((RM >> 24) & 0xFF); + } + // REV16 + else if (op1 == 0x03 && op2 == 0x05) { + RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) | ((RM & 0xFF000000) >> 8); + } + // REVSH + else if (op1 == 0x07 && op2 == 0x05) { + RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8); + if (RD & 0x8000) + RD |= 0xffff0000; + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(rev_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + RFE_INST: + { + // RFE is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address, 1); + + cpu->Cpsr = ARMul_LoadWordN(cpu, address); + cpu->Reg[15] = ARMul_LoadWordN(cpu, address + 4); + + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + + RSB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + rsb_inst* const inst_cream = (rsb_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * GET_INST_SIZE(cpu); + + bool carry; + bool overflow; + RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(rsb_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(rsb_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + RSC_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + rsc_inst* const inst_cream = (rsc_inst*)inst_base->component; + + bool carry; + bool overflow; + RD = AddWithCarry(~RN, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(rsc_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(rsc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SADD8_INST: + SSUB8_INST: + SADD16_INST: + SADDSUBX_INST: + SSUBADDX_INST: + SSUB16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u8 op2 = inst_cream->op2; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { + const s16 rn_lo = (RN & 0xFFFF); + const s16 rn_hi = ((RN >> 16) & 0xFFFF); + const s16 rm_lo = (RM & 0xFFFF); + const s16 rm_hi = ((RM >> 16) & 0xFFFF); + + s32 lo_result = 0; + s32 hi_result = 0; + + // SADD16 + if (inst_cream->op2 == 0x00) { + lo_result = (rn_lo + rm_lo); + hi_result = (rn_hi + rm_hi); + } + // SASX + else if (op2 == 0x01) { + lo_result = (rn_lo - rm_hi); + hi_result = (rn_hi + rm_lo); + } + // SSAX + else if (op2 == 0x02) { + lo_result = (rn_lo + rm_hi); + hi_result = (rn_hi - rm_lo); + } + // SSUB16 + else if (op2 == 0x03) { + lo_result = (rn_lo - rm_lo); + hi_result = (rn_hi - rm_hi); + } + + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + + if (lo_result >= 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } + + if (hi_result >= 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + else if (op2 == 0x04 || op2 == 0x07) { + s32 lo_val1, lo_val2; + s32 hi_val1, hi_val2; + + // SADD8 + if (op2 == 0x04) { + lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF); + lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF); + hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF); + hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF); + } + // SSUB8 + else { + lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF); + lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF); + hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF); + hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF); + } + + RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24)); + + if (lo_val1 >= 0) + cpu->Cpsr |= (1 << 16); + else + cpu->Cpsr &= ~(1 << 16); + + if (lo_val2 >= 0) + cpu->Cpsr |= (1 << 17); + else + cpu->Cpsr &= ~(1 << 17); + + if (hi_val1 >= 0) + cpu->Cpsr |= (1 << 18); + else + cpu->Cpsr &= ~(1 << 18); + + if (hi_val2 >= 0) + cpu->Cpsr |= (1 << 19); + else + cpu->Cpsr &= ~(1 << 19); + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SBC_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sbc_inst* const inst_cream = (sbc_inst*)inst_base->component; + + bool carry; + bool overflow; + RD = AddWithCarry(RN, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(sbc_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sbc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SEL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u32 to = RM; + const u32 from = RN; + const u32 cpsr = cpu->Cpsr; + + u32 result; + if (cpsr & (1 << 16)) + result = from & 0xff; + else + result = to & 0xff; + + if (cpsr & (1 << 17)) + result |= from & 0x0000ff00; + else + result |= to & 0x0000ff00; + + if (cpsr & (1 << 18)) + result |= from & 0x00ff0000; + else + result |= to & 0x00ff0000; + + if (cpsr & (1 << 19)) + result |= from & 0xff000000; + else + result |= to & 0xff000000; + + RD = result; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SETEND_INST: + { + // SETEND is unconditional + setend_inst* const inst_cream = (setend_inst*)inst_base->component; + const bool big_endian = (inst_cream->set_bigend == 1); + + if (big_endian) + cpu->Cpsr |= (1 << 9); + else + cpu->Cpsr &= ~(1 << 9); + + LOG("SETEND %s executed", big_endian ? "BE" : "LE"); + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(setend_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SHADD8_INST: + SHADD16_INST: + SHADDSUBX_INST: + SHSUB8_INST: + SHSUB16_INST: + SHSUBADDX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { + s32 lo_result = 0; + s32 hi_result = 0; + + // SHADD16 + if (op2 == 0x00) { + lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + } + // SHASX + else if (op2 == 0x01) { + lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; + } + // SHSAX + else if (op2 == 0x02) { + lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; + } + // SHSUB16 + else if (op2 == 0x03) { + lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + } + + RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16)); + } + else if (op2 == 0x04 || op2 == 0x07) { + s16 lo_val1, lo_val2; + s16 hi_val1, hi_val2; + + // SHADD8 + if (op2 == 0x04) { + lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1; + lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1; + + hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1; + hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1; + } + // SHSUB8 + else { + lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1; + lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1; + + hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1; + hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1; + } + + RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24); + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLA_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smla_inst* inst_cream = (smla_inst*)inst_base->component; + int32_t operand1, operand2; + if (inst_cream->x == 0) + operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); + else + operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); + + if (inst_cream->y == 0) + operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); + else + operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); + RD = operand1 * operand2 + RN; + + if (AddOverflow(operand1 * operand2, RN, RD)) + cpu->Cpsr |= (1 << 27); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smla_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLAD_INST: + SMLSD_INST: + SMUAD_INST: + SMUSD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + const u8 op2 = inst_cream->op2; + + u32 rm_val = cpu->Reg[inst_cream->Rm]; + const u32 rn_val = cpu->Reg[inst_cream->Rn]; + + if (inst_cream->m) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + + const s16 rm_lo = (rm_val & 0xFFFF); + const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); + const s16 rn_lo = (rn_val & 0xFFFF); + const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); + + const u32 product1 = (rn_lo * rm_lo); + const u32 product2 = (rn_hi * rm_hi); + + // SMUAD and SMLAD + if (BIT(op2, 1) == 0) { + RD = (product1 + product2); + + if (inst_cream->Ra != 15) { + RD += cpu->Reg[inst_cream->Ra]; + + if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) + cpu->Cpsr |= (1 << 27); + } + + if (ARMul_AddOverflowQ(product1, product2)) + cpu->Cpsr |= (1 << 27); + } + // SMUSD and SMLSD + else { + RD = (product1 - product2); + + if (inst_cream->Ra != 15) { + RD += cpu->Reg[inst_cream->Ra]; + + if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) + cpu->Cpsr |= (1 << 27); + } + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLAL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; + long long int rm = RM; + long long int rs = RS; + if (BIT(rm, 31)) { + rm |= 0xffffffff00000000LL; + } + if (BIT(rs, 31)) { + rs |= 0xffffffff00000000LL; + } + long long int rst = rm * rs; + long long int rdhi32 = RDHI; + long long int hilo = (rdhi32 << 32) + RDLO; + rst += hilo; + RDLO = BITS(rst, 0, 31); + RDHI = BITS(rst, 32, 63); + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(umlal_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLALXY_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; + + u64 operand1 = RN; + u64 operand2 = RM; + + if (inst_cream->x != 0) + operand1 >>= 16; + if (inst_cream->y != 0) + operand2 >>= 16; + operand1 &= 0xFFFF; + if (operand1 & 0x8000) + operand1 -= 65536; + operand2 &= 0xFFFF; + if (operand2 & 0x8000) + operand2 -= 65536; + + u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2); + RDLO = (dest & 0xFFFFFFFF); + RDHI = ((dest >> 32) & 0xFFFFFFFF); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlalxy_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLAW_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + const u32 rm_val = RM; + const u32 rn_val = RN; + const u32 ra_val = cpu->Reg[inst_cream->Ra]; + const bool high = (inst_cream->m == 1); + + const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); + const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); + + RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16; + + if ((result >> 16) != (s32)RD) + cpu->Cpsr |= (1 << 27); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMLALD_INST: + SMLSLD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; + + const bool do_swap = (inst_cream->swap == 1); + const u32 rdlo_val = RDLO; + const u32 rdhi_val = RDHI; + const u32 rn_val = RN; + u32 rm_val = RM; + + if (do_swap) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + + const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF); + const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF); + s64 result; + + // SMLALD + if (BIT(inst_cream->op2, 1) == 0) { + result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); + } + // SMLSLD + else { + result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); + } + + RDLO = (result & 0xFFFFFFFF); + RDHI = ((result >> 32) & 0xFFFFFFFF); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlald_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMMLA_INST: + SMMLS_INST: + SMMUL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + const u32 rm_val = RM; + const u32 rn_val = RN; + const bool do_round = (inst_cream->m == 1); + + // Assume SMMUL by default. + s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val; + + if (inst_cream->Ra != 15) { + const u32 ra_val = cpu->Reg[inst_cream->Ra]; + + // SMMLA, otherwise SMMLS + if (BIT(inst_cream->op2, 1) == 0) + result += ((s64)ra_val << 32); + else + result = ((s64)ra_val << 32) - result; + } + + if (do_round) + result += 0x80000000; + + RD = ((result >> 32) & 0xFFFFFFFF); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMUL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smul_inst* inst_cream = (smul_inst*)inst_base->component; + uint32_t operand1, operand2; + if (inst_cream->x == 0) + operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); + else + operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); + + if (inst_cream->y == 0) + operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); + else + operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); + RD = operand1 * operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smul_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SMULL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; + int64_t rm = RM; + int64_t rs = RS; + if (BIT(rm, 31)) { + rm |= 0xffffffff00000000LL; + } + if (BIT(rs, 31)) { + rs |= 0xffffffff00000000LL; + } + int64_t rst = rm * rs; + RDHI = BITS(rst, 32, 63); + RDLO = BITS(rst, 0, 31); + + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(umull_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SMULW_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); + + s64 result = (s64)rm * (s64)(s32)RN; + RD = BITS(result, 16, 47); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SRS_INST: + { + // SRS is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address, 1); + + ARMul_StoreWordN(cpu, address + 0, cpu->Reg[14]); + ARMul_StoreWordN(cpu, address + 4, cpu->Spsr_copy); + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SSAT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + + u8 shift_type = inst_cream->shift_type; + u8 shift_amount = inst_cream->imm5; + u32 rn_val = RN; + + // 32-bit ASR is encoded as an amount of 0. + if (shift_type == 1 && shift_amount == 0) + shift_amount = 31; + + if (shift_type == 0) + rn_val <<= shift_amount; + else if (shift_type == 1) + rn_val = ((s32)rn_val >> shift_amount); + + bool saturated = false; + rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated); + + if (saturated) + cpu->Cpsr |= (1 << 27); + + RD = rn_val; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SSAT16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + const u8 saturate_to = inst_cream->sat_imm; + + bool sat1 = false; + bool sat2 = false; + + RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | + ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; + + if (sat1 || sat2) + cpu->Cpsr |= (1 << 27); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + STC_INST: + { + // Instruction not implemented + //LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(stc_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STM_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + unsigned int inst = inst_cream->inst; + + unsigned int Rn = BITS(inst, 16, 19); + unsigned int old_RN = cpu->Reg[Rn]; + + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + if (BIT(inst_cream->inst, 22) == 1) { + for (int i = 0; i < 13; i++) { + if (BIT(inst_cream->inst, i)) { + ARMul_StoreWordN(cpu, addr, cpu->Reg[i]); + addr += 4; + } + } + if (BIT(inst_cream->inst, 13)) { + if (cpu->Mode == USER32MODE) + ARMul_StoreWordN(cpu, addr, cpu->Reg[13]); + else + ARMul_StoreWordN(cpu, addr, cpu->Reg_usr[0]); + + addr += 4; + } + if (BIT(inst_cream->inst, 14)) { + if (cpu->Mode == USER32MODE) + ARMul_StoreWordN(cpu, addr, cpu->Reg[14]); + else + ARMul_StoreWordN(cpu, addr, cpu->Reg_usr[1]); + + addr += 4; + } + if (BIT(inst_cream->inst, 15)) { + ARMul_StoreWordN(cpu, addr, cpu->Reg_usr[1] + 8); + } + } else { + for (int i = 0; i < 15; i++) { + if (BIT(inst_cream->inst, i)) { + if (i == Rn) + ARMul_StoreWordN(cpu, addr, old_RN); + else + ARMul_StoreWordN(cpu, addr, cpu->Reg[i]); + + addr += 4; + } + } + + // Check PC reg + if (BIT(inst_cream->inst, 15)) + ARMul_StoreWordN(cpu, addr, cpu->Reg_usr[1] + 8); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SXTB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); + if (BIT(operand2, 7)) { + operand2 |= 0xffffff00; + } else { + operand2 &= 0xff; + } + RD = operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sxtb_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STR_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; + ARMul_StoreWordN(cpu, addr, value); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UXTB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxtb_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UXTAB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + RD = RN + operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STRB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; + ARMul_StoreByte(cpu,addr, value); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STRBT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; + ARMul_StoreByte(cpu, addr, value); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STRD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + + // The 3DS doesn't have the Large Physical Access Extension (LPAE) + // so STRD wouldn't store these as a single write. + ARMul_StoreWordN(cpu, addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]); + ARMul_StoreWordN(cpu, addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + + ARMul_StoreWordN(cpu, write_addr, RM); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREXB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + + ARMul_StoreByte(cpu, write_addr, cpu->Reg[inst_cream->Rm]); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREXD_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + + const u32 rt = cpu->Reg[inst_cream->Rm + 0]; + const u32 rt2 = cpu->Reg[inst_cream->Rm + 1]; + u64 value; + + value = (((u64)rt2 << 32) | rt); + + ARMul_WriteDouble(cpu, write_addr, value); + RD = 0; + } + else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREXH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + + ARMul_StoreHalfWord(cpu, write_addr, RM); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STRH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; + ARMul_StoreHalfWord(cpu, addr, value); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STRT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; + ARMul_StoreWordN(cpu, addr, value); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SUB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sub_inst* const inst_cream = (sub_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 8; + + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + switch_mode(cpu, cpu->Spsr_copy & 0x1f); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(sub_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sub_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SWI_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + + ProcessSwi(BITS(ARMul_LoadInstrS(cpu, cpu->Reg[15],4), 0, 24), state->Reg, state->m_currentThread); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(swi_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SWP_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; + + addr = RN; + unsigned int value = ARMul_LoadWordN(cpu, addr); + ARMul_StoreWordN(cpu, addr, RM); + + RD = value; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(swp_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SWPB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; + addr = RN; + unsigned int value = ARMul_LoadByte(cpu,addr); + ARMul_StoreByte(cpu,addr, (RM & 0xFF)); + RD = value; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(swp_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + SXTAB_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + + // Sign extend for byte + operand2 = (0x80 & operand2)? (0xFFFFFF00 | operand2):operand2; + RD = RN + operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SXTAB16_INST: + SXTB16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; + + const u8 rotation = inst_cream->rotate * 8; + u32 rm_val = RM; + u32 rn_val = RN; + + if (rotation) + rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); + + // SXTB16 + if (inst_cream->Rn == 15) { + u32 lo = (u32)(s8)rm_val; + u32 hi = (u32)(s8)(rm_val >> 16); + RD = (lo | (hi << 16)); + } + // SXTAB16 + else { + u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF); + u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF); + RD = (lo | (hi << 16)); + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + SXTAH_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + // Sign extend for half + operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2; + RD = RN + operand2; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(sxtah_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + TEQ_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + teq_inst* const inst_cream = (teq_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + + if (inst_cream->Rn == 15) + lop += GET_INST_SIZE(cpu) * 2; + + u32 result = lop ^ rop; + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + UPDATE_CFLAG_WITH_SC; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(teq_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + TST_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + tst_inst* const inst_cream = (tst_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + + if (inst_cream->Rn == 15) + lop += GET_INST_SIZE(cpu) * 2; + + u32 result = lop & rop; + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + UPDATE_CFLAG_WITH_SC; + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(tst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + UADD8_INST: + UADD16_INST: + UADDSUBX_INST: + USUB8_INST: + USUB16_INST: + USUBADDX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; + + s32 lo_result = 0; + s32 hi_result = 0; + + // UADD16 + if (op2 == 0x00) { + lo_result = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + + if (lo_result & 0xFFFF0000) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } + + if (hi_result & 0xFFFF0000) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // UASX + else if (op2 == 0x01) { + lo_result = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); + + if (lo_result >= 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } + + if (hi_result >= 0x10000) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // USAX + else if (op2 == 0x02) { + lo_result = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); + + if (lo_result >= 0x10000) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } + + if (hi_result >= 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // USUB16 + else if (op2 == 0x03) { + lo_result = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + + if ((lo_result & 0xFFFF0000) == 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } + + if ((hi_result & 0xFFFF0000) == 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // UADD8 + else if (op2 == 0x04) { + s16 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); + s16 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); + s16 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); + s16 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); + + if (sum1 >= 0x100) + state->Cpsr |= (1 << 16); + else + state->Cpsr &= ~(1 << 16); + + if (sum2 >= 0x100) + state->Cpsr |= (1 << 17); + else + state->Cpsr &= ~(1 << 17); + + if (sum3 >= 0x100) + state->Cpsr |= (1 << 18); + else + state->Cpsr &= ~(1 << 18); + + if (sum4 >= 0x100) + state->Cpsr |= (1 << 19); + else + state->Cpsr &= ~(1 << 19); + + lo_result = ((sum1 & 0xFF) | (sum2 & 0xFF) << 8); + hi_result = ((sum3 & 0xFF) | (sum4 & 0xFF) << 8); + } + // USUB8 + else if (op2 == 0x07) { + s16 diff1 = (rn_val & 0xFF) - (rm_val & 0xFF); + s16 diff2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); + s16 diff3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); + s16 diff4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); + + if (diff1 >= 0) + state->Cpsr |= (1 << 16); + else + state->Cpsr &= ~(1 << 16); + + if (diff2 >= 0) + state->Cpsr |= (1 << 17); + else + state->Cpsr &= ~(1 << 17); + + if (diff3 >= 0) + state->Cpsr |= (1 << 18); + else + state->Cpsr &= ~(1 << 18); + + if (diff4 >= 0) + state->Cpsr |= (1 << 19); + else + state->Cpsr &= ~(1 << 19); + + lo_result = (diff1 & 0xFF) | ((diff2 & 0xFF) << 8); + hi_result = (diff3 & 0xFF) | ((diff4 & 0xFF) << 8); + } + + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + UHADD8_INST: + UHADD16_INST: + UHADDSUBX_INST: + UHSUBADDX_INST: + UHSUB8_INST: + UHSUB16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u32 rm_val = RM; + const u32 rn_val = RN; + const u8 op2 = inst_cream->op2; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) + { + u32 lo_val = 0; + u32 hi_val = 0; + + // UHADD16 + if (op2 == 0x00) { + lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + } + // UHASX + else if (op2 == 0x01) { + lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); + } + // UHSAX + else if (op2 == 0x02) { + lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); + } + // UHSUB16 + else if (op2 == 0x03) { + lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + } + + lo_val >>= 1; + hi_val >>= 1; + + RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16); + } + else if (op2 == 0x04 || op2 == 0x07) { + u32 sum1; + u32 sum2; + u32 sum3; + u32 sum4; + + // UHADD8 + if (op2 == 0x04) { + sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); + } + // UHSUB8 + else { + sum1 = (rn_val & 0xFF) - (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); + } + + sum1 >>= 1; + sum2 >>= 1; + sum3 >>= 1; + sum4 >>= 1; + + RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24); + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + UMAAL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; + const u64 rm = RM; + const u64 rn = RN; + const u64 rd_lo = RDLO; + const u64 rd_hi = RDHI; + const u64 result = (rm * rn) + rd_lo + rd_hi; + + RDLO = (result & 0xFFFFFFFF); + RDHI = ((result >> 32) & 0xFFFFFFFF); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(umaal_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UMLAL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; + unsigned long long int rm = RM; + unsigned long long int rs = RS; + unsigned long long int rst = rm * rs; + unsigned long long int add = ((unsigned long long) RDHI)<<32; + add += RDLO; + rst += add; + RDLO = BITS(rst, 0, 31); + RDHI = BITS(rst, 32, 63); + + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(umlal_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + UMULL_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; + unsigned long long int rm = RM; + unsigned long long int rs = RS; + unsigned long long int rst = rm * rs; + RDHI = BITS(rst, 32, 63); + RDLO = BITS(rst, 0, 31); + + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(umull_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + B_2_THUMB: + { + b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; + cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; + INC_PC(sizeof(b_2_thumb)); + goto DISPATCH; + } + B_COND_THUMB: + { + b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component; + + if(CondPassed(cpu, inst_cream->cond)) + cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; + else + cpu->Reg[15] += 2; + + INC_PC(sizeof(b_cond_thumb)); + goto DISPATCH; + } + BL_1_THUMB: + { + bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component; + cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm; + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bl_1_thumb)); + FETCH_INST; + GOTO_NEXT_INST; + } + BL_2_THUMB: + { + bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component; + int tmp = ((cpu->Reg[15] + 2) | 1); + cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm); + cpu->Reg[14] = tmp; + INC_PC(sizeof(bl_2_thumb)); + goto DISPATCH; + } + BLX_1_THUMB: + { + // BLX 1 for armv5t and above + u32 tmp = cpu->Reg[15]; + blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component; + cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC; + cpu->Reg[14] = ((tmp + 2) | 1); + cpu->TFlag = 0; + INC_PC(sizeof(blx_1_thumb)); + goto DISPATCH; + } + + UQADD8_INST: + UQADD16_INST: + UQADDSUBX_INST: + UQSUB8_INST: + UQSUB16_INST: + UQSUBADDX_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; + + u16 lo_val = 0; + u16 hi_val = 0; + + // UQADD16 + if (op2 == 0x00) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQASX + else if (op2 == 0x01) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSAX + else if (op2 == 0x02) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSUB16 + else if (op2 == 0x03) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQADD8 + else if (op2 == 0x04) { + lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8; + } + // UQSUB8 + else { + lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) | + ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8; + } + + RD = ((lo_val & 0xFFFF) | hi_val << 16); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + USAD8_INST: + USADA8_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 ra_idx = inst_cream->Ra; + const u32 rm_val = RM; + const u32 rn_val = RN; + + const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF); + const u8 diff2 = ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF); + const u8 diff3 = ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF); + const u8 diff4 = ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF); + + u32 finalDif = (diff1 + diff2 + diff3 + diff4); + + // Op is USADA8 if true. + if (ra_idx != 15) + finalDif += cpu->Reg[ra_idx]; + + RD = finalDif; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + USAT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + + u8 shift_type = inst_cream->shift_type; + u8 shift_amount = inst_cream->imm5; + u32 rn_val = RN; + + // 32-bit ASR is encoded as an amount of 0. + if (shift_type == 1 && shift_amount == 0) + shift_amount = 31; + + if (shift_type == 0) + rn_val <<= shift_amount; + else if (shift_type == 1) + rn_val = ((s32)rn_val >> shift_amount); + + bool saturated = false; + rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated); + + if (saturated) + cpu->Cpsr |= (1 << 27); + + RD = rn_val; + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + USAT16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + const u8 saturate_to = inst_cream->sat_imm; + + bool sat1 = false; + bool sat2 = false; + + RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | + ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; + + if (sat1 || sat2) + cpu->Cpsr |= (1 << 27); + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + UXTAB16_INST: + UXTB16_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; + + const u8 rn_idx = inst_cream->Rn; + const u32 rm_val = RM; + const u32 rotation = inst_cream->rotate * 8; + const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); + + // UXTB16, otherwise UXTAB16 + if (rn_idx == 15) { + RD = rotated_rm & 0x00FF00FF; + } else { + const u32 rn_val = RN; + const u8 lo_rotated = (rotated_rm & 0xFF); + const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated; + const u8 hi_rotated = (rotated_rm >> 16) & 0xFF; + const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated; + + RD = ((hi_result << 16) | (lo_result & 0xFFFF)); + } + } + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + + #define VFP_INTERPRETER_IMPL + #include "arm/skyeye_common/vfp/vfpinstr.cpp" + #undef VFP_INTERPRETER_IMPL + + END: + { + SAVE_NZCVT; + cpu->NumInstrsToExecute = 0; + return num_instrs; + } + INIT_INST_LENGTH: + { + cpu->NumInstrsToExecute = 0; + return num_instrs; + } +} diff --git a/source/arm/dyncom/arm_dyncom_interpreter.h b/source/arm/dyncom/arm_dyncom_interpreter.h new file mode 100644 index 0000000..4791ea2 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_interpreter.h @@ -0,0 +1,7 @@ +// Copyright 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +unsigned InterpreterMainLoop(ARMul_State* state); diff --git a/source/arm/dyncom/arm_dyncom_run.cpp b/source/arm/dyncom/arm_dyncom_run.cpp new file mode 100644 index 0000000..0e1eb58 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_run.cpp @@ -0,0 +1,98 @@ +// Copyright 2012 Michael Kang, 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +//massive fixed by ichfly XDS/3dmoo team + +#include +#include "Kernel.h" + +#include "arm/dyncom/arm_dyncom_run.h" +#include "arm/skyeye_common/armdefs.h" + +void switch_mode(ARMul_State* core, uint32_t mode) { + if (core->Mode == mode) + return; + + if (mode != USERBANK) { + switch (core->Mode) { + case SYSTEM32MODE: // Shares registers with user mode + case USER32MODE: + core->Reg_usr[0] = core->Reg[13]; + core->Reg_usr[1] = core->Reg[14]; + break; + case IRQ32MODE: + core->Reg_irq[0] = core->Reg[13]; + core->Reg_irq[1] = core->Reg[14]; + core->Spsr[IRQBANK] = core->Spsr_copy; + break; + case SVC32MODE: + core->Reg_svc[0] = core->Reg[13]; + core->Reg_svc[1] = core->Reg[14]; + core->Spsr[SVCBANK] = core->Spsr_copy; + break; + case ABORT32MODE: + core->Reg_abort[0] = core->Reg[13]; + core->Reg_abort[1] = core->Reg[14]; + core->Spsr[ABORTBANK] = core->Spsr_copy; + break; + case UNDEF32MODE: + core->Reg_undef[0] = core->Reg[13]; + core->Reg_undef[1] = core->Reg[14]; + core->Spsr[UNDEFBANK] = core->Spsr_copy; + break; + case FIQ32MODE: + core->Reg_firq[0] = core->Reg[13]; + core->Reg_firq[1] = core->Reg[14]; + core->Spsr[FIQBANK] = core->Spsr_copy; + break; + } + + switch (mode) { + case USER32MODE: + core->Reg[13] = core->Reg_usr[0]; + core->Reg[14] = core->Reg_usr[1]; + core->Bank = USERBANK; + break; + case IRQ32MODE: + core->Reg[13] = core->Reg_irq[0]; + core->Reg[14] = core->Reg_irq[1]; + core->Spsr_copy = core->Spsr[IRQBANK]; + core->Bank = IRQBANK; + break; + case SVC32MODE: + core->Reg[13] = core->Reg_svc[0]; + core->Reg[14] = core->Reg_svc[1]; + core->Spsr_copy = core->Spsr[SVCBANK]; + core->Bank = SVCBANK; + break; + case ABORT32MODE: + core->Reg[13] = core->Reg_abort[0]; + core->Reg[14] = core->Reg_abort[1]; + core->Spsr_copy = core->Spsr[ABORTBANK]; + core->Bank = ABORTBANK; + break; + case UNDEF32MODE: + core->Reg[13] = core->Reg_undef[0]; + core->Reg[14] = core->Reg_undef[1]; + core->Spsr_copy = core->Spsr[UNDEFBANK]; + core->Bank = UNDEFBANK; + break; + case FIQ32MODE: + core->Reg[13] = core->Reg_firq[0]; + core->Reg[14] = core->Reg_firq[1]; + core->Spsr_copy = core->Spsr[FIQBANK]; + core->Bank = FIQBANK; + break; + case SYSTEM32MODE: // Shares registers with user mode. + core->Reg[13] = core->Reg_usr[0]; + core->Reg[14] = core->Reg_usr[1]; + core->Bank = SYSTEMBANK; + break; + } + + // Set the mode bits in the APSR + core->Cpsr = (core->Cpsr & ~core->Mode) | mode; + core->Mode = mode; + } +} diff --git a/source/arm/dyncom/arm_dyncom_run.h b/source/arm/dyncom/arm_dyncom_run.h new file mode 100644 index 0000000..bbc23c7 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_run.h @@ -0,0 +1,55 @@ +/* Copyright (C) +* 2011 - Michael.Kang blackfin.kang@gmail.com +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +* +*/ + +#ifndef __ARM_DYNCOM_RUN__ +#define __ARM_DYNCOM_RUN__ + +#include "arm/skyeye_common/skyeye_types.h" + +void switch_mode(arm_core_t *core, uint32_t mode); + +/* FIXME, we temporarily think thumb instruction is always 16 bit */ +static inline u32 GET_INST_SIZE(arm_core_t* core) { + return core->TFlag? 2 : 4; +} + +/** +* @brief Read R15 and forced R15 to wold align, used address calculation +* +* @param core +* @param Rn +* +* @return +*/ +static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) { + return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; +} + +/** +* @brief Read R15, used to data processing with pc +* +* @param core +* @param Rn +* +* @return +*/ +static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) { + return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; +} + +#endif diff --git a/source/arm/dyncom/arm_dyncom_supp.cpp b/source/arm/dyncom/arm_dyncom_supp.cpp new file mode 100644 index 0000000..7b3e925 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_supp.cpp @@ -0,0 +1,46 @@ +#include "Kernel.h" +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/arm_regformat.h" + +u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) +{ + // Unprivileged registers + if (crn == 13 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 2) + return cpu->CP15[CP15(CP15_THREAD_UPRW)]; + + // TODO: Whenever TLS is implemented, this should return + // "cpu->CP15[CP15(CP15_THREAD_URO)];" + // which contains the address of the 0x200-byte TLS + if (opcode_2 == 3) + return cpu->m_currentThread->m_TSL3DS; + } + + LOG("MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2); + return 0; +} + +// Write to the CP15 registers. Used with implementation of the MCR instruction. +// Note that since the 3DS does not have the hypervisor extensions, these registers +// are not implemented. +void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) +{ + // Unprivileged registers + if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) + { + cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value; + } + else if (crn == 7 && opcode_1 == 0 && crm == 10) + { + if (opcode_2 == 4) + cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value; + else if (opcode_2 == 5) + cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value; + + } + else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) + { + cpu->CP15[CP15(CP15_THREAD_UPRW)] = value; + } +} diff --git a/source/arm/dyncom/arm_dyncom_thumb.cpp b/source/arm/dyncom/arm_dyncom_thumb.cpp new file mode 100644 index 0000000..7cf3858 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_thumb.cpp @@ -0,0 +1,459 @@ +// Copyright 2012 Michael Kang, 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +//massive fixed by ichfly XDS/3dmoo team + +// We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding +// ARM instruction, and using the existing ARM simulator. + +#include "Kernel.h" + +#include "arm/skyeye_common/skyeye_defs.h" + +#ifndef MODET // Required for the Thumb instruction support +#if 1 +#error "MODET needs to be defined for the Thumb world to work" +#else +#define MODET (1) +#endif +#endif + +//#include "Kernel.h" + +#include "arm/skyeye_common/armos.h" +#include "arm/dyncom/arm_dyncom_thumb.h" + +// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, +// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions +// allows easier simulation of the special dual BL instruction. + +//they are different in here +#define BIT(data,n) ( (ARMword)(data>>(n))&1) /* bit n of instruction */ +#define BITS(data,m,n) ( (ARMword)(data<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ + + +tdstate thumb_translate(addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) { + tdstate valid = t_uninitialized; + ARMword tinstr; + tinstr = instr; + + // The endian should be judge here + if ((addr & 0x3) != 0) + tinstr = instr >> 16; + else + tinstr &= 0xFFFF; + + *ainstr = 0xDEADC0DE; // Debugging to catch non updates + + switch ((tinstr & 0xF800) >> 11) { + case 0: // LSL + case 1: // LSR + case 2: // ASR + *ainstr = 0xE1B00000 // base opcode + | ((tinstr & 0x1800) >> (11 - 5)) // shift type + | ((tinstr & 0x07C0) << (7 - 6)) // imm5 + | ((tinstr & 0x0038) >> 3) // Rs + | ((tinstr & 0x0007) << 12); // Rd + break; + + case 3: // ADD/SUB + { + ARMword subset[4] = { + 0xE0900000, // ADDS Rd,Rs,Rn + 0xE0500000, // SUBS Rd,Rs,Rn + 0xE2900000, // ADDS Rd,Rs,#imm3 + 0xE2500000 // SUBS Rd,Rs,#imm3 + }; + // It is quicker indexing into a table, than performing switch or conditionals: + *ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode + | ((tinstr & 0x01C0) >> 6) // Rn or imm3 + | ((tinstr & 0x0038) << (16 - 3)) // Rs + | ((tinstr & 0x0007) << (12 - 0)); // Rd + } + break; + + case 4: // MOV + case 5: // CMP + case 6: // ADD + case 7: // SUB + { + ARMword subset[4] = { + 0xE3B00000, // MOVS Rd,#imm8 + 0xE3500000, // CMP Rd,#imm8 + 0xE2900000, // ADDS Rd,Rd,#imm8 + 0xE2500000, // SUBS Rd,Rd,#imm8 + }; + + *ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode + | ((tinstr & 0x00FF) >> 0) // imm8 + | ((tinstr & 0x0700) << (16 - 8)) // Rn + | ((tinstr & 0x0700) << (12 - 8)); // Rd + } + break; + + case 8: // Arithmetic and high register transfers + + // TODO: Since the subsets for both Format 4 and Format 5 instructions are made up of + // different ARM encodings, we could save the following conditional, and just have one + // large subset + + if ((tinstr & (1 << 10)) == 0) { + enum otype { + t_norm, + t_shift, + t_neg, + t_mul + }; + + struct { + ARMword opcode; + otype type; + } subset[16] = { + { 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs + { 0xE0300000, t_norm }, // EORS Rd,Rd,Rs + { 0xE1B00010, t_shift }, // MOVS Rd,Rd,LSL Rs + { 0xE1B00030, t_shift }, // MOVS Rd,Rd,LSR Rs + { 0xE1B00050, t_shift }, // MOVS Rd,Rd,ASR Rs + { 0xE0B00000, t_norm }, // ADCS Rd,Rd,Rs + { 0xE0D00000, t_norm }, // SBCS Rd,Rd,Rs + { 0xE1B00070, t_shift }, // MOVS Rd,Rd,ROR Rs + { 0xE1100000, t_norm }, // TST Rd,Rs + { 0xE2700000, t_neg }, // RSBS Rd,Rs,#0 + { 0xE1500000, t_norm }, // CMP Rd,Rs + { 0xE1700000, t_norm }, // CMN Rd,Rs + { 0xE1900000, t_norm }, // ORRS Rd,Rd,Rs + { 0xE0100090, t_mul }, // MULS Rd,Rd,Rs + { 0xE1D00000, t_norm }, // BICS Rd,Rd,Rs + { 0xE1F00000, t_norm } // MVNS Rd,Rs + }; + + *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base + + switch (subset[(tinstr & 0x03C0) >> 6].type) { + case t_norm: + *ainstr |= ((tinstr & 0x0007) << 16) // Rn + | ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0038) >> 3); // Rs + break; + case t_shift: + *ainstr |= ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0007) >> 0) // Rm + | ((tinstr & 0x0038) << (8 - 3)); // Rs + break; + case t_neg: + *ainstr |= ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0038) << (16 - 3)); // Rn + break; + case t_mul: + *ainstr |= ((tinstr & 0x0007) << 16) // Rd + | ((tinstr & 0x0007) << 8) // Rs + | ((tinstr & 0x0038) >> 3); // Rm + break; + } + } + else { + ARMword Rd = ((tinstr & 0x0007) >> 0); + ARMword Rs = ((tinstr & 0x0038) >> 3); + + if (tinstr & (1 << 7)) + Rd += 8; + if (tinstr & (1 << 6)) + Rs += 8; + + switch ((tinstr & 0x03C0) >> 6) { + case 0x0: /* ADD Rd,Rd,Hs */ + case 0x1: /* ADD Rd,Rd,Hs */ + case 0x2: /* ADD Rd,Rd,Hs */ + case 0x3: /* ADD Rd,Rd,Hs */ + *ainstr = 0xE0800000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + + case 0x4: /* CMP Rd,Hs */ + case 0x5: /* CMP Rd,Hs */ + case 0x6: /* CMP Hd,Rs */ + case 0x7: /* CMP Hd,Hs */ + *ainstr = 0xE1500000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0x8: /* MOV Rd,Hs */ + case 0x9: /* MOV Rd,Hs */ + case 0xA: /* MOV Hd,Rs */ + case 0xB: /* MOV Hd,Hs */ + *ainstr = 0xE1A00000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0xC: /* BX Rs */ + case 0xD: /* BX Hs */ + *ainstr = 0xE12FFF10 /* base */ + | ((tinstr & 0x0078) >> 3); /* Rd */ + break; + case 0xE: /* BLX */ + case 0xF: /* BLX */ + *ainstr = 0xE1200030 /* base */ + | (Rs << 0); /* Rm */ + break; + } + } + break; + + case 9: // LDR Rd,[PC,#imm8] + *ainstr = 0xE59F0000 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | ((tinstr & 0x00FF) << (2 - 0)); // off8 + break; + + case 10: + case 11: + { + static const ARMword subset[8] = { + 0xE7800000, // STR Rd,[Rb,Ro] + 0xE18000B0, // STRH Rd,[Rb,Ro] + 0xE7C00000, // STRB Rd,[Rb,Ro] + 0xE19000D0, // LDRSB Rd,[Rb,Ro] + 0xE7900000, // LDR Rd,[Rb,Ro] + 0xE19000B0, // LDRH Rd,[Rb,Ro] + 0xE7D00000, // LDRB Rd,[Rb,Ro] + 0xE19000F0 // LDRSH Rd,[Rb,Ro] + }; + + *ainstr = subset[(tinstr & 0xE00) >> 9] // base + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x01C0) >> 6); // Ro + break; + } + + case 12: // STR Rd,[Rb,#imm5] + case 13: // LDR Rd,[Rb,#imm5] + case 14: // STRB Rd,[Rb,#imm5] + case 15: // LDRB Rd,[Rb,#imm5] + { + ARMword subset[4] = { + 0xE5800000, // STR Rd,[Rb,#imm5] + 0xE5900000, // LDR Rd,[Rb,#imm5] + 0xE5C00000, // STRB Rd,[Rb,#imm5] + 0xE5D00000 // LDRB Rd,[Rb,#imm5] + }; + // The offset range defends on whether we are transferring a byte or word value: + *ainstr = subset[(tinstr & 0x1800) >> 11] // base + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5 + } + break; + + case 16: // STRH Rd,[Rb,#imm5] + case 17: // LDRH Rd,[Rb,#imm5] + *ainstr = ((tinstr & (1 << 11)) // base + ? 0xE1D000B0 // LDRH + : 0xE1C000B0) // STRH + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble + | ((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble + break; + + case 18: // STR Rd,[SP,#imm8] + case 19: // LDR Rd,[SP,#imm8] + *ainstr = ((tinstr & (1 << 11)) // base + ? 0xE59D0000 // LDR + : 0xE58D0000) // STR + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | ((tinstr & 0x00FF) << 2); // off8 + break; + + case 20: // ADD Rd,PC,#imm8 + case 21: // ADD Rd,SP,#imm8 + + if ((tinstr & (1 << 11)) == 0) { + + // NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the + // rotate immediate field, so no shift of off8 is needed. + + *ainstr = 0xE28F0F00 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | (tinstr & 0x00FF); // off8 + } + else { + // We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed. + *ainstr = 0xE28D0F00 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | (tinstr & 0x00FF); // off8 + } + break; + + case 22: + case 23: + if ((tinstr & 0x0F00) == 0x0000) { + // NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30): + *ainstr = ((tinstr & (1 << 7)) // base + ? 0xE24DDF00 // SUB + : 0xE28DDF00) // ADD + | (tinstr & 0x007F); // off7 + } + else if ((tinstr & 0x0F00) == 0x0E00) { + // BKPT T1 + *ainstr = 0xEF000000 // base + | BITS(tinstr, 0, 3) // imm4 field; + | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12 + } + else if ((tinstr & 0x0F00) == 0x600) { + if (BIT(tinstr, 5) == 0) { + // SETEND T1 + *ainstr = 0xF1010000 // base + | (BIT(tinstr, 3) << 9); // endian specifier + } + else { + // CPS T1 + *ainstr = 0xF1080000 // base + | (BIT(tinstr, 0) << 6) // fiq bit + | (BIT(tinstr, 1) << 7) // irq bit + | (BIT(tinstr, 2) << 8) // abort bit + | (BIT(tinstr, 4) << 18); // enable bit + } + } + else if ((tinstr & 0x0F00) == 0x0a00) { + static const ARMword subset[3] = { + 0xE6BF0F30, // REV T1 + 0xE6BF0FB0, // REV16 T1 + 0xE6FF0FB0, // REVSH T1 + }; + + *ainstr = subset[BITS(tinstr, 6, 7)] // base + | (BITS(tinstr, 0, 2) << 12) // Rd + | BITS(tinstr, 3, 5); // Rm + } + else if ((tinstr & 0x600) == 0x400) + { + /* Format 14 */ + u32 subset[4] = { + 0xE92D0000, /* STMDB sp!,{rlist} */ + 0xE92D4000, /* STMDB sp!,{rlist,lr} */ + 0xE8BD0000, /* LDMIA sp!,{rlist} */ + 0xE8BD8000 /* LDMIA sp!,{rlist,pc} */ + }; + *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */ + | (tinstr & 0x00FF); /* mask8 */ + } + else + { + //e6bf1071 sxth r1, r1 + //e6af1071 sxtb r1, r1 + //e6ff1078 uxth r1, r8 + //e6ef1078 uxtb r1, r8 + + u32 subset[4] = { //Bit 12 - 15 dest Bit 0 - 3 src + 0xe6ff0070, /* uxth */ + 0xe6ef0070, /* uxtb */ + 0xe6bf0070, /* sxth */ + 0xe6af0070 /* sxtb */ + }; + + if ((tinstr & 0xF00) == 0x200) //Bit(7) unsigned (set = sxt. cleared = uxt) Bit(6) byte (set = .xtb cleared = .xth) Bit 5-3 Rb src Bit 2-0 Rd dest + { + *ainstr = subset[((tinstr & (0x3 << 6)) >> 6)] | + (tinstr & 0x7) << 12 | + (tinstr & 0x38) >> 3; + } + else if ((tinstr & 0x0FC0) == 0x0A00){ + u32 Destr = (tinstr & 0x7); + u32 srcr = ((tinstr >> 3) & 0x7); + *ainstr = 0xE6BF0F30 | srcr | (Destr << 12); + + } + else + { + valid = t_undefined; + XDSERROR("unk thumb instr %04x", tinstr); + } + + } + break; + + case 24: // STMIA + case 25: // LDMIA + { + u32 Rb = (tinstr & 0x0700) >> 8; + if ((1 << Rb)&tinstr) //no write back if the register is in the list + { + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE8900000 /* LDMIA */ + : 0xE8800000) /* STMIA */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rb */ + | (tinstr & 0x00FF); /* mask8 */ + break; + } + else + { + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE8B00000 /* LDMIA */ + : 0xE8A00000) /* STMIA */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rb */ + | (tinstr & 0x00FF); /* mask8 */ + break; + } + } + + case 26: // Bcc + case 27: // Bcc/SWI + if ((tinstr & 0x0F00) == 0x0F00) { + // Format 17 : SWI + *ainstr = 0xEF000000; + // Breakpoint must be handled specially. + if ((tinstr & 0x00FF) == 0x18) + *ainstr |= ((tinstr & 0x00FF) << 16); + // New breakpoint value. See gdb/arm-tdep.c + else if ((tinstr & 0x00FF) == 0xFE) + *ainstr |= SWI_Breakpoint; + else + *ainstr |= (tinstr & 0x00FF); + } + else if ((tinstr & 0x0F00) != 0x0E00) + valid = t_branch; + else // UNDEFINED : cc=1110(AL) uses different format + valid = t_undefined; + + break; + + case 28: // B + valid = t_branch; + break; + + case 29: + if (tinstr & 0x1) + valid = t_undefined; + else + valid = t_branch; + break; + + case 30: // BL instruction 1 + + // There is no single ARM instruction equivalent for this Thumb instruction. To keep the + // simulation simple (from the user perspective) we check if the following instruction is + // the second half of this BL, and if it is we simulate it immediately + + valid = t_branch; + break; + + case 31: // BL instruction 2 + + // There is no single ARM instruction equivalent for this instruction. Also, it should only + // ever be matched with the fmt19 "BL instruction 1" instruction. However, we do allow the + // simulation of it on its own, with undefined results if r14 is not suitably initialised. + + valid = t_branch; + break; + } + + *inst_size = 2; + + return valid; +} \ No newline at end of file diff --git a/source/arm/dyncom/arm_dyncom_thumb.h b/source/arm/dyncom/arm_dyncom_thumb.h new file mode 100644 index 0000000..b4d6858 --- /dev/null +++ b/source/arm/dyncom/arm_dyncom_thumb.h @@ -0,0 +1,53 @@ +/* Copyright (C) +* 2011 - Michael.Kang blackfin.kang@gmail.com +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +* +*/ + +/** +* @file arm_dyncom_thumb.h +* @brief The thumb dyncom +* @author Michael.Kang blackfin.kang@gmail.com +* @version 78.77 +* @date 2011-11-07 +*/ + +#ifndef __ARM_DYNCOM_THUMB_H__ +#define __ARM_DYNCOM_THUMB_H__ + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/skyeye_types.h" + +#ifndef _ARM_INTERPRETER_H +enum tdstate { + t_undefined, // Undefined Thumb instruction + t_decoded, // Instruction decoded to ARM equivalent + t_branch, // Thumb branch (already processed) + t_uninitialized, +}; +#endif + +tdstate thumb_translate(addr_t addr, u32 instr, u32* ainstr, u32* inst_size); + +static inline u32 get_thumb_instr(u32 instr, addr_t pc) { + u32 tinstr; + if ((pc & 0x3) != 0) + tinstr = instr >> 16; + else + tinstr = instr & 0xFFFF; + return tinstr; +} + +#endif diff --git a/source/arm/interpreter/arm_interpreter.cpp b/source/arm/interpreter/arm_interpreter.cpp new file mode 100644 index 0000000..f1069e8 --- /dev/null +++ b/source/arm/interpreter/arm_interpreter.cpp @@ -0,0 +1,117 @@ +// Copyright 2014 Citra Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "Kernel.h" + +//#include "core.h" + +const static cpu_config_t arm11_cpu_info = { + "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE +}; + +ARM_Interpreter::ARM_Interpreter() { + + state = new ARMul_State; + state->m_MemoryMap = NULL; + + + ARMul_EmulateInit(); + memset(state, 0, sizeof(ARMul_State)); + + ARMul_NewState(state); + + state->abort_model = 0; + state->cpu = (cpu_config_t*)&arm11_cpu_info; + state->bigendSig = LOW; + + ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); + state->lateabtSig = LOW; + + // Reset the core to initial state + ARMul_CoProInit(state); + ARMul_Reset(state); + state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext + state->Emulate = 3; + + state->pc = state->Reg[15] = 0x00000000; + state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack + state->servaddr = 0xFFFF0000; +} + +ARM_Interpreter::~ARM_Interpreter() { + delete state; +} + +void ARM_Interpreter::SetPC(u32 pc) { + state->pc = state->Reg[15] = pc; +} + +u32 ARM_Interpreter::GetPC() const { + return state->pc; +} + +u32 ARM_Interpreter::GetReg(int index) const { + return state->Reg[index]; +} + +void ARM_Interpreter::SetReg(int index, u32 value) { + state->Reg[index] = value; +} + +u32 ARM_Interpreter::GetCPSR() const { + return state->Cpsr; +} + +void ARM_Interpreter::SetCPSR(u32 cpsr) { + state->Cpsr = cpsr; +} + +u64 ARM_Interpreter::GetTicks() const { + return state->NumInstrs; +} + +void ARM_Interpreter::AddTicks(u64 ticks) { + state->NumInstrs += ticks; +} + +u64 ARM_Interpreter::ExecuteInstructions(int num_instructions) { + state->NumInstrsToExecute = num_instructions - 1; + return ARMul_Emulate32(state); +} + +void ARM_Interpreter::SaveContext(ThreadContext& ctx) { + memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); + memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); + + ctx.sp = state->Reg[13]; + ctx.lr = state->Reg[14]; + ctx.pc = state->pc; + ctx.cpsr = state->Cpsr; + + ctx.fpscr = state->VFP[1]; + ctx.fpexc = state->VFP[2]; + + ctx.reg_15 = state->Reg[15]; + ctx.mode = state->NextInstr; +} + +void ARM_Interpreter::LoadContext(const ThreadContext& ctx) { + memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); + memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); + + state->Reg[13] = ctx.sp; + state->Reg[14] = ctx.lr; + state->pc = ctx.pc; + state->Cpsr = ctx.cpsr; + + state->VFP[1] = ctx.fpscr; + state->VFP[2] = ctx.fpexc; + + state->Reg[15] = ctx.reg_15; + state->NextInstr = ctx.mode; +} + +void ARM_Interpreter::PrepareReschedule() { + state->NumInstrsToExecute = 0; +} diff --git a/source/arm/interpreter/arm_interpreter.h b/source/arm/interpreter/arm_interpreter.h new file mode 100644 index 0000000..778cbf5 --- /dev/null +++ b/source/arm/interpreter/arm_interpreter.h @@ -0,0 +1,94 @@ + + +#ifndef _ARM_INTERPRETER_H +#define _ARM_INTERPRETER_H + +#include "Common.h" + +#include "arm/arm_interface.h" +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" + +class ARM_Interpreter final : virtual public ARM_Interface { +public: + + ARM_Interpreter(); + ~ARM_Interpreter(); + + /** + * Set the Program Counter to an address + * @param pc Address to set PC to + */ + void SetPC(u32 pc) override; + + /* + * Get the current Program Counter + * @return Returns current PC + */ + u32 GetPC() const override; + + /** + * Get an ARM register + * @param index Register index (0-15) + * @return Returns the value in the register + */ + u32 GetReg(int index) const override; + + /** + * Set an ARM register + * @param index Register index (0-15) + * @param value Value to set register to + */ + void SetReg(int index, u32 value) override; + + /** + * Get the current CPSR register + * @return Returns the value of the CPSR register + */ + u32 GetCPSR() const override; + + /** + * Set the current CPSR register + * @param cpsr Value to set CPSR to + */ + void SetCPSR(u32 cpsr) override; + + /** + * Returns the number of clock ticks since the last reset + * @return Returns number of clock ticks + */ + u64 GetTicks() const override; + + /** + * Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time) + * @param ticks Number of ticks to advance the CPU core + */ + void AddTicks(u64 ticks) override; + + /** + * Saves the current CPU context + * @param ctx Thread context to save + */ + void SaveContext(ThreadContext& ctx) override; + + /** + * Loads a CPU context + * @param ctx Thread context to load + */ + void LoadContext(const ThreadContext& ctx) override; + + /// Prepare core for thread reschedule (if needed to correctly handle state) + void PrepareReschedule() override; + ARMul_State* state; + +protected: + + /** + * Executes the given number of instructions + * @param num_instructions Number of instructions to executes + */ + u64 ExecuteInstructions(int num_instructions) override; + + +}; +#endif diff --git a/source/arm/interpreter/armcopro.cpp b/source/arm/interpreter/armcopro.cpp new file mode 100644 index 0000000..9c0c6ad --- /dev/null +++ b/source/arm/interpreter/armcopro.cpp @@ -0,0 +1,327 @@ +/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator. + Copyright (C) 1994, 2000 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "Kernel.h" + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" +#include "arm/skyeye_common/vfp/vfp.h" + +//chy 2005-07-08 +//#include "ansidecl.h" +//chy ------- +//#include "iwmmxt.h" + +/* Dummy Co-processors. */ + +static unsigned +NoCoPro3R(ARMul_State * state, +unsigned a, ARMword b) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro4R(ARMul_State * state, +unsigned a, +ARMword b, ARMword c) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro4W(ARMul_State * state, +unsigned a, +ARMword b, ARMword * c) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro5R(ARMul_State * state, +unsigned a, +ARMword b, +ARMword c, ARMword d) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro5W(ARMul_State * state, +unsigned a, +ARMword b, +ARMword * c, ARMword * d) +{ + return ARMul_CANT; +} + +/* The XScale Co-processors. */ + +/* Coprocessor 15: System Control. */ +static void write_cp14_reg(unsigned, ARMword); +static ARMword read_cp14_reg(unsigned); + +/* Check an access to a register. */ + +static unsigned +check_cp15_access(ARMul_State * state, +unsigned reg, +unsigned CRm, unsigned opcode_1, unsigned opcode_2) +{ + /* Do not allow access to these register in USER mode. */ + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (state->Mode == USER26MODE || state->Mode == USER32MODE) + return ARMul_CANT; + + /* Opcode_1should be zero. */ + if (opcode_1 != 0) + return ARMul_CANT; + + /* Different register have different access requirements. */ + switch (reg) { + case 0: + case 1: + /* CRm must be 0. Opcode_2 can be anything. */ + if (CRm != 0) + return ARMul_CANT; + break; + case 2: + case 3: + /* CRm must be 0. Opcode_2 must be zero. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 4: + /* Access not allowed. */ + return ARMul_CANT; + case 5: + case 6: + /* Opcode_2 must be zero. CRm must be 0. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 7: + /* Permissable combinations: + Opcode_2 CRm + 0 5 + 0 6 + 0 7 + 1 5 + 1 6 + 1 10 + 4 10 + 5 2 + 6 5 */ + switch (opcode_2) { + default: + return ARMul_CANT; + case 6: + if (CRm != 5) + return ARMul_CANT; + break; + case 5: + if (CRm != 2) + return ARMul_CANT; + break; + case 4: + if (CRm != 10) + return ARMul_CANT; + break; + case 1: + if ((CRm != 5) && (CRm != 6) && (CRm != 10)) + return ARMul_CANT; + break; + case 0: + if ((CRm < 5) || (CRm > 7)) + return ARMul_CANT; + break; + } + break; + + case 8: + /* Permissable combinations: + Opcode_2 CRm + 0 5 + 0 6 + 0 7 + 1 5 + 1 6 */ + if (opcode_2 > 1) + return ARMul_CANT; + if ((CRm < 5) || (CRm > 7)) + return ARMul_CANT; + if (opcode_2 == 1 && CRm == 7) + return ARMul_CANT; + break; + case 9: + /* Opcode_2 must be zero or one. CRm must be 1 or 2. */ + if (((CRm != 0) && (CRm != 1)) + || ((opcode_2 != 1) && (opcode_2 != 2))) + return ARMul_CANT; + break; + case 10: + /* Opcode_2 must be zero or one. CRm must be 4 or 8. */ + if (((CRm != 0) && (CRm != 1)) + || ((opcode_2 != 4) && (opcode_2 != 8))) + return ARMul_CANT; + break; + case 11: + /* Access not allowed. */ + return ARMul_CANT; + case 12: + /* Access not allowed. */ + return ARMul_CANT; + case 13: + /* Opcode_2 must be zero. CRm must be 0. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 14: + /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */ + if (opcode_2 != 0) + return ARMul_CANT; + + if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) + && (CRm != 9)) + return ARMul_CANT; + break; + case 15: + /* Opcode_2 must be zero. CRm must be 1. */ + if ((CRm != 1) || (opcode_2 != 0)) + return ARMul_CANT; + break; + default: + /* Should never happen. */ + return ARMul_CANT; + } + + return ARMul_DONE; +} + +/* Install co-processor instruction handlers in this routine. */ + +unsigned +ARMul_CoProInit(ARMul_State * state) +{ + unsigned int i; + + /* Initialise tham all first. */ + for (i = 0; i < 16; i++) + ARMul_CoProDetach(state, i); + + /* Install CoPro Instruction handlers here. + The format is: + ARMul_CoProAttach (state, CP Number, Init routine, Exit routine + LDC routine, STC routine, MRC routine, MCR routine, + CDP routine, Read Reg routine, Write Reg routine). */ + if (state->is_v6) { + ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC, + VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); + ARMul_CoProAttach(state, 11, VFPInit, NULL, VFPLDC, VFPSTC, + VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); + + /*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, + MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/ + } + //chy 2003-09-03 do it in future!!!!???? +#if 0 + if (state->is_iWMMXt) { + ARMul_CoProAttach(state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC, + NULL, NULL, IwmmxtCDP, NULL, NULL); + + ARMul_CoProAttach(state, 1, NULL, NULL, NULL, NULL, + IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, + NULL); + } +#endif + /* No handlers below here. */ + + /* Call all the initialisation routines. */ + for (i = 0; i < 16; i++) + if (state->CPInit[i]) + (state->CPInit[i]) (state); + + return TRUE; +} + +/* Install co-processor finalisation routines in this routine. */ + +void +ARMul_CoProExit(ARMul_State * state) +{ + register unsigned i; + + for (i = 0; i < 16; i++) + if (state->CPExit[i]) + (state->CPExit[i]) (state); + + for (i = 0; i < 16; i++) /* Detach all handlers. */ + ARMul_CoProDetach(state, i); +} + +/* Routines to hook Co-processors into ARMulator. */ + +void +ARMul_CoProAttach(ARMul_State * state, +unsigned number, +ARMul_CPInits * init, +ARMul_CPExits * exit, +ARMul_LDCs * ldc, +ARMul_STCs * stc, +ARMul_MRCs * mrc, +ARMul_MCRs * mcr, +ARMul_MRRCs * mrrc, +ARMul_MCRRs * mcrr, +ARMul_CDPs * cdp, +ARMul_CPReads * read, ARMul_CPWrites * write) +{ + if (init != NULL) + state->CPInit[number] = init; + if (exit != NULL) + state->CPExit[number] = exit; + if (ldc != NULL) + state->LDC[number] = ldc; + if (stc != NULL) + state->STC[number] = stc; + if (mrc != NULL) + state->MRC[number] = mrc; + if (mcr != NULL) + state->MCR[number] = mcr; + if (mrrc != NULL) + state->MRRC[number] = mrrc; + if (mcrr != NULL) + state->MCRR[number] = mcrr; + if (cdp != NULL) + state->CDP[number] = cdp; + if (read != NULL) + state->CPRead[number] = read; + if (write != NULL) + state->CPWrite[number] = write; +} + +void +ARMul_CoProDetach(ARMul_State * state, unsigned number) +{ + ARMul_CoProAttach(state, number, NULL, NULL, + NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, + NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL); + + state->CPInit[number] = NULL; + state->CPExit[number] = NULL; + state->CPRead[number] = NULL; + state->CPWrite[number] = NULL; +} diff --git a/source/arm/interpreter/armemu.cpp b/source/arm/interpreter/armemu.cpp new file mode 100644 index 0000000..03c94cb --- /dev/null +++ b/source/arm/interpreter/armemu.cpp @@ -0,0 +1,6559 @@ +/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + Modifications to add arch. v4 support by . + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +//#include // DEBUG() + +#include "Kernel.h" + +#include "arm/skyeye_common/arm_regformat.h" +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" + +#include "arm/memory.h" + +//#include "hle/hle.h" +//#include "svc.h" + +//ichfly +//#define callstacker 1 + +//#include "skyeye_callback.h" +//#include "skyeye_bus.h" +//#include "sim_control.h" +//#include "skyeye_pref.h" +//#include "skyeye.h" +//#include "skyeye2gdb.h" +//#include "code_cov.h" + +//#include "iwmmxt.h" +//chy 2003-07-11: for debug instrs +//extern int skyeye_instr_debug; +extern FILE *skyeye_logfd; + +static ARMword GetDPRegRHS (ARMul_State *, ARMword); +static ARMword GetDPSRegRHS (ARMul_State *, ARMword); +static void WriteR15 (ARMul_State *, ARMword); +static void WriteSR15 (ARMul_State *, ARMword); +static void WriteR15Branch (ARMul_State *, ARMword); +static ARMword GetLSRegRHS (ARMul_State *, ARMword); +static ARMword GetLS7RHS (ARMul_State *, ARMword); +static unsigned LoadWord (ARMul_State *, ARMword, ARMword); +static unsigned LoadHalfWord (ARMul_State *, ARMword, ARMword, int); +static unsigned LoadByte (ARMul_State *, ARMword, ARMword, int); +static unsigned StoreWord (ARMul_State *, ARMword, ARMword); +static unsigned StoreHalfWord (ARMul_State *, ARMword, ARMword); +static unsigned StoreByte (ARMul_State *, ARMword, ARMword); +static void LoadMult (ARMul_State *, ARMword, ARMword, ARMword); +static void StoreMult (ARMul_State *, ARMword, ARMword, ARMword); +static void LoadSMult (ARMul_State *, ARMword, ARMword, ARMword); +static void StoreSMult (ARMul_State *, ARMword, ARMword, ARMword); +static unsigned Multiply64 (ARMul_State *, ARMword, int, int); +static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int); +static void Handle_Load_Double (ARMul_State *, ARMword); +static void Handle_Store_Double (ARMul_State *, ARMword); + +static int +handle_v6_insn (ARMul_State * state, ARMword instr); + +#define LUNSIGNED (0) /* unsigned operation */ +#define LSIGNED (1) /* signed operation */ +#define LDEFAULT (0) /* default : do nothing */ +#define LSCC (1) /* set condition codes on result */ + +#ifdef NEED_UI_LOOP_HOOK +/* How often to run the ui_loop update, when in use. */ +#define UI_LOOP_POLL_INTERVAL 0x32000 + +/* Counter for the ui_loop_hook update. */ +static int ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + +/* Actual hook to call to run through gdb's gui event loop. */ +extern int (*ui_loop_hook) (int); +#endif /* NEED_UI_LOOP_HOOK */ + +/* Short-hand macros for LDR/STR. */ + +/* Store post decrement writeback. */ +#define SHDOWNWB() \ + lhs = LHS ; \ + if (StoreHalfWord (state, instr, lhs)) \ + LSBase = lhs - GetLS7RHS (state, instr); + +/* Store post increment writeback. */ +#define SHUPWB() \ + lhs = LHS ; \ + if (StoreHalfWord (state, instr, lhs)) \ + LSBase = lhs + GetLS7RHS (state, instr); + +/* Store pre decrement. */ +#define SHPREDOWN() \ + (void)StoreHalfWord (state, instr, LHS - GetLS7RHS (state, instr)); + +/* Store pre decrement writeback. */ +#define SHPREDOWNWB() \ + temp = LHS - GetLS7RHS (state, instr); \ + if (StoreHalfWord (state, instr, temp)) \ + LSBase = temp; + +/* Store pre increment. */ +#define SHPREUP() \ + (void)StoreHalfWord (state, instr, LHS + GetLS7RHS (state, instr)); + +/* Store pre increment writeback. */ +#define SHPREUPWB() \ + temp = LHS + GetLS7RHS (state, instr); \ + if (StoreHalfWord (state, instr, temp)) \ + LSBase = temp; + +/* Load post decrement writeback. */ +#define LHPOSTDOWN() \ +{ \ + int done = 1; \ + lhs = LHS; \ + temp = lhs - GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load post increment writeback. */ +#define LHPOSTUP() \ +{ \ + int done = 1; \ + lhs = LHS; \ + temp = lhs + GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre decrement. */ +#define LHPREDOWN() \ +{ \ + int done = 1; \ + \ + temp = LHS - GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ + break; \ + case 2: /* SB */ \ + (void) LoadByte (state, instr, temp, LSIGNED); \ + break; \ + case 3: /* SH */ \ + (void) LoadHalfWord (state, instr, temp, LSIGNED); \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre decrement writeback. */ +#define LHPREDOWNWB() \ +{ \ + int done = 1; \ + \ + temp = LHS - GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre increment. */ +#define LHPREUP() \ +{ \ + int done = 1; \ + \ + temp = LHS + GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ + break; \ + case 2: /* SB */ \ + (void) LoadByte (state, instr, temp, LSIGNED); \ + break; \ + case 3: /* SH */ \ + (void) LoadHalfWord (state, instr, temp, LSIGNED); \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre increment writeback. */ +#define LHPREUPWB() \ +{ \ + int done = 1; \ + \ + temp = LHS + GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/*ywc 2005-03-31*/ +//teawater add for arm2x86 2005.02.17------------------------------------------- +#ifdef DBCT +#include "dbct/tb.h" +#include "dbct/arm2x86_self.h" +#endif +//AJ2D-------------------------------------------------------------------------- + +//Diff register +unsigned int mirror_register_file[39]; + +/* EMULATION of ARM6. */ + +extern int debugmode; +int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr); +#ifdef MODE32 +//chy 2006-04-12, for ICE debug +int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr) +{ + return 0; +} + +static int dump = 0; +ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr) +{ + /*printf("[%08x] ", pc); + arm11_Disasm32(pc);*/ + + /*if (pc >= 0x0010303C && pc <= 0x00103050) + { + printf("[%08x] = %08X = ", pc, instr); + arm11_Disasm32(pc); + arm11_Dump(); + }*/ + + //fprintf(stderr,"[%08x]\n", pc); + + //if (pc == 0x00240C88) + // arm11_Dump(); + + /*if (pc == 0x188e04) + { + DEBUG("read %08X %08X %016X %08X %08X from %08X", state->Reg[0], state->Reg[1], state->Reg[2] | state->Reg[3] << 32, mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] + 4), state->Reg[14]); + } + if (pc == 0x21222c) + { + arm11_Dump(); + mem_Dbugdump(); + }*/ + + /*if (pc == 0x0022D168) + { + int j = 0; + }*/ + + /*if (state->Reg[4] == 0x00105734) + { + printf("[%08x] ", pc); + arm11_Disasm32(pc); + }*/ + + return 0; +} + +/* +void chy_debug() +{ + printf("SkyEye chy_deubeg begin\n"); +} +*/ +ARMword +ARMul_Emulate32 (ARMul_State * state) +#else +ARMword +ARMul_Emulate26 (ARMul_State * state) +#endif +{ + /* The PC pipeline value depends on whether ARM + or Thumb instructions are being + d. */ + ARMword isize; + ARMword instr; /* The current instruction. */ + ARMword dest = 0; /* Almost the DestBus. */ + ARMword temp; /* Ubiquitous third hand. */ + ARMword pc = 0; /* The address of the current instruction. */ + ARMword lhs; /* Almost the ABus and BBus. */ + ARMword rhs; + ARMword decoded = 0; /* Instruction pipeline. */ + ARMword loaded = 0; + ARMword decoded_addr=0; + ARMword loaded_addr=0; + ARMword have_bp=0; + +#ifdef callstacker + char a[256]; +#endif + /* shenoubang */ + static int instr_sum = 0; + int reg_index = 0; +#if DIFF_STATE +//initialize all mirror register for follow mode + for (reg_index = 0; reg_index < 16; reg_index ++) { + mirror_register_file[reg_index] = state->Reg[reg_index]; + } + mirror_register_file[CPSR_REG] = state->Cpsr; + mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; + mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; + mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13]; + mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14]; + mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13]; + mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14]; + mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13]; + mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14]; + mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8]; + mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9]; + mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10]; + mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11]; + mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12]; + mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13]; + mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14]; + mirror_register_file[SPSR_SVC] = state->Spsr[SVCBANK]; + mirror_register_file[SPSR_ABORT] = state->Spsr[ABORTBANK]; + mirror_register_file[SPSR_UNDEF] = state->Spsr[UNDEFBANK]; + mirror_register_file[SPSR_IRQ] = state->Spsr[IRQBANK]; + mirror_register_file[SPSR_FIRQ] = state->Spsr[FIQBANK]; +#endif + /* Execute the next instruction. */ + if (state->NextInstr < PRIMEPIPE) { + decoded = state->decoded; + loaded = state->loaded; + pc = state->pc; + //chy 2006-04-12, for ICE debug + decoded_addr=state->decoded_addr; + loaded_addr=state->loaded_addr; + } + + do { + //print_func_name(state->pc); + /* Just keep going. */ + isize = INSN_SIZE; + + switch (state->NextInstr) { + case SEQ: + /* Advance the pipeline, and an S cycle. */ + state->Reg[15] += isize; + pc += isize; + instr = decoded; + //chy 2006-04-12, for ICE debug + have_bp = ARMul_ICE_debug(state,instr,decoded_addr); + decoded = loaded; + decoded_addr=loaded_addr; + //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), + // isize); + loaded_addr=pc + (isize * 2); + if (have_bp) goto TEST_EMULATE; + break; + + case NONSEQ: + /* Advance the pipeline, and an N cycle. */ + state->Reg[15] += isize; + pc += isize; + instr = decoded; + //chy 2006-04-12, for ICE debug + have_bp=ARMul_ICE_debug(state,instr,decoded_addr); + decoded = loaded; + decoded_addr=loaded_addr; + //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), + // isize); + loaded_addr=pc + (isize * 2); + NORMALCYCLE; + if (have_bp) goto TEST_EMULATE; + break; + + case PCINCEDSEQ: + /* Program counter advanced, and an S cycle. */ + pc += isize; + instr = decoded; + //chy 2006-04-12, for ICE debug + have_bp=ARMul_ICE_debug(state,instr,decoded_addr); + decoded = loaded; + decoded_addr=loaded_addr; + //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), + // isize); + loaded_addr=pc + (isize * 2); + NORMALCYCLE; + if (have_bp) goto TEST_EMULATE; + break; + + case PCINCEDNONSEQ: + /* Program counter advanced, and an N cycle. */ + pc += isize; + instr = decoded; + //chy 2006-04-12, for ICE debug + have_bp=ARMul_ICE_debug(state,instr,decoded_addr); + decoded = loaded; + decoded_addr=loaded_addr; + //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), + // isize); + loaded_addr=pc + (isize * 2); + NORMALCYCLE; + if (have_bp) goto TEST_EMULATE; + break; + + case RESUME: + /* The program counter has been changed. */ + pc = state->Reg[15]; +#ifndef MODE32 + pc = pc & R15PCBITS; +#endif + state->Reg[15] = pc + (isize * 2); + state->Aborted = 0; + //chy 2004-05-25, fix bug provided by Carl van Schaik + state->AbortAddr = 1; + + instr = ARMul_LoadInstrN (state, pc, isize); + //instr = ARMul_ReLoadInstr (state, pc, isize); + //chy 2006-04-12, for ICE debug + have_bp=ARMul_ICE_debug(state,instr,pc); + //decoded = + // ARMul_ReLoadInstr (state, pc + isize, isize); + decoded_addr=pc+isize; + //loaded = ARMul_ReLoadInstr (state, pc + isize * 2, + // isize); + loaded_addr=pc + isize * 2; + NORMALCYCLE; + if (have_bp) goto TEST_EMULATE; + break; + + default: + /* The program counter has been changed. */ + pc = state->Reg[15]; +#ifndef MODE32 + pc = pc & R15PCBITS; +#endif + state->Reg[15] = pc + (isize * 2); + state->Aborted = 0; + //chy 2004-05-25, fix bug provided by Carl van Schaik + state->AbortAddr = 1; + + instr = ARMul_LoadInstrN (state, pc, isize); + + //chy 2006-04-12, for ICE debug + have_bp=ARMul_ICE_debug(state,instr,pc); +#if 0 + decoded = + ARMul_LoadInstrS (state, pc + (isize), isize); +#endif + decoded_addr=pc+isize; +#if 0 + loaded = ARMul_LoadInstrS (state, pc + (isize * 2), + isize); +#endif + loaded_addr=pc + isize * 2; + NORMALCYCLE; + if (have_bp) goto TEST_EMULATE; + break; + } +#if 0 + int idx = 0; + printf("pc:%x\n", pc); + for (; idx < 17; idx ++) { + printf("R%d:%x\t", idx, state->Reg[idx]); + } + printf("\n"); +#endif + + instr = ARMul_LoadInstrN (state, pc, isize); + state->last_instr = state->CurrInstr; + state->CurrInstr = instr; + ARMul_Debug(state, pc, instr); +#if 0 + if((state->NumInstrs % 10000000) == 0) + printf("---|%p|--- %lld\n", pc, state->NumInstrs); + if(state->NumInstrs > (3000000000)) { + static int flag = 0; + if(pc == 0x8032ccc4) { + flag = 300; + } + if(flag) { + int idx = 0; + printf("------------------------------------\n"); + printf("pc:%x\n", pc); + for (; idx < 17; idx ++) { + printf("R%d:%x\t", idx, state->Reg[idx]); + } + printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag); + printf("\n"); + printf("------------------------------------\n"); + flag--; + } + } +#endif +#if DIFF_STATE + fprintf(state->state_log, "PC:0x%x\n", pc); + if (pc && (pc + 8) != state->Reg[15]) { + printf("lucky dog\n"); + printf("pc is %x, R15 is %x\n", pc, state->Reg[15]); + //exit(-1); + } + for (reg_index = 0; reg_index < 16; reg_index ++) { + if (state->Reg[reg_index] != mirror_register_file[reg_index]) { + fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]); + mirror_register_file[reg_index] = state->Reg[reg_index]; + } + } + if (state->Cpsr != mirror_register_file[CPSR_REG]) { + fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr); + mirror_register_file[CPSR_REG] = state->Cpsr; + } + if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) { + fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]); + mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; + } + if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) { + fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]); + mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; + } + if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) { + fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]); + mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13]; + } + if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) { + fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]); + mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14]; + } + if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) { + fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]); + mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13]; + } + if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) { + fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]); + mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14]; + } + if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) { + fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]); + mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13]; + } + if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) { + fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]); + mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14]; + } + if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) { + fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]); + mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8]; + } + if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) { + fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]); + mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9]; + } + if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) { + fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]); + mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10]; + } + if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) { + fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]); + mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11]; + } + if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) { + fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]); + mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12]; + } + if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) { + fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]); + mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13]; + } + if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) { + fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]); + mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14]; + } + if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) { + fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]); + mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK]; + } + if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) { + fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]); + mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK]; + } + if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) { + fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]); + mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK]; + } + if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) { + fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]); + mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK]; + } + if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) { + fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]); + mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK]; + } +#endif + +#if 0 + uint32_t alex = 0; + static int flagged = 0; + if ((flagged == 0) && (pc == 0xb224)) { + flagged++; + } + if ((flagged == 1) && (pc == 0x1a800)) { + flagged++; + } + if (flagged == 3) { + printf("---|%p|--- %x\n", pc, state->NumInstrs); + for (alex = 0; alex < 15; alex++) { + printf("R%02d % 8x\n", alex, state->Reg[alex]); + } + printf("R%02d % 8x\n", alex, state->Reg[alex] - 8); + printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff); + } else { + if (state->NumInstrs < 0x400000) { + //exit(-1); + } + } +#endif + + /*if (state->EventSet) + ARMul_EnvokeEvent (state);*/ + +#if 0 + /* do profiling for code coverage */ + if (skyeye_config.code_cov.prof_on) + cov_prof(EXEC_FLAG, pc); +#endif +//2003-07-11 chy: for test +#if 0 + if (skyeye_config.log.logon >= 1) { + if (state->NumInstrs >= skyeye_config.log.start && + state->NumInstrs <= skyeye_config.log.end) { + static int mybegin = 0; + static int myinstrnum = 0; + if (mybegin == 0) + mybegin = 1; +#if 0 + if (state->NumInstrs == 3695) { + printf ("***********SKYEYE: numinstr = 3695\n"); + } + static int mybeg2 = 0; + static int mybeg3 = 0; + static int mybeg4 = 0; + static int mybeg5 = 0; + + if (pc == 0xa0008000) { + //mybegin=1; + printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs); + } + + //chy 2003-09-02 test fiq + if (state->NumInstrs == 67347000) { + printf ("***********SKYEYE: numinstr = 67347000, begin log\n"); + mybegin = 1; + } + if (pc == 0xc00087b4) { //numinstr=67348714 + mybegin = 1; + printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs); + } + if (pc == 0xc00087b8) { //in start_kernel::sti() + mybeg4 = 1; + printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs); + } + /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */ + if (pc == 0xc001e500) { //MRA instr + mybeg5 = 1; + printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs); + } + if (pc >= 0xc0000000 && mybeg2 == 0) { + mybeg2 = 1; + printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs); + SKYEYE_OUTREGS (stderr); + printf ("************************************************************************\n"); + } + //chy 2003-09-01 test after tlb-flush + if (pc == 0xc00261ac) { + //sleep(2); + mybeg3 = 1; + printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs); + } + if (mybeg3 == 1) { + SKYEYE_OUTREGS (skyeye_logfd); + SKYEYE_OUTMOREREGS (skyeye_logfd); + fprintf (skyeye_logfd, "\n"); + } +#endif + if (mybegin == 1) { + //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded); + //chy for test 20050729 + /*if (state->NumInstrs>=3302294) { + if (pc==0x100c9d4 && instr==0xe1b0f00e){ + chy_debug(); + printf("*********************************************\n"); + printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr); + printf("*********************************************\n"); + } + */ + if (skyeye_config.log.logon >= 1) + /* + fprintf (skyeye_logfd, + "N %llx :p %x,i %x,", + state->NumInstrs, pc, + #ifdef MODET + TFLAG ? instr & 0xffff : instr + #else + instr + #endif + ); + */ + fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]); + if (skyeye_config.log.logon >= 2) + SKYEYE_OUTREGS (skyeye_logfd); + if (skyeye_config.log.logon >= 3) + SKYEYE_OUTMOREREGS + (skyeye_logfd); + //fprintf (skyeye_logfd, "\n"); + if (skyeye_config.log.length > 0) { + myinstrnum++; + if (myinstrnum >= + skyeye_config.log. + length) { + myinstrnum = 0; + fflush (skyeye_logfd); + fseek (skyeye_logfd, + 0L, SEEK_SET); + } + } + } + //SKYEYE_OUTREGS(skyeye_logfd); + //SKYEYE_OUTMOREREGS(skyeye_logfd); + } + } +#endif +#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ + fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); + if (instr == 0) + abort (); +#endif +#if 0 /* Enable this code to help track down stack alignment bugs. */ + { + static ARMword old_sp = -1; + + if (old_sp != state->Reg[13]) { + old_sp = state->Reg[13]; + fprintf (stderr, + "pc: %08x: SP set to %08x%s\n", + pc & ~1, old_sp, + (old_sp % 8) ? " [UNALIGNED!]" : ""); + } + } +#endif + /* Any exceptions ? */ + if (state->NresetSig == LOW) { + ARMul_Abort (state, ARMul_ResetV); + + /*added energy_prof statement by ksh in 2004-11-26 */ + //chy 2005-07-28 for standalone + //ARMul_do_energy(state,instr,pc); + break; + } else if (!state->NfiqSig && !FFLAG) { + ARMul_Abort (state, ARMul_FIQV); + /*added energy_prof statement by ksh in 2004-11-26 */ + //chy 2005-07-28 for standalone + //ARMul_do_energy(state,instr,pc); + break; + } else if (!state->NirqSig && !IFLAG) { + ARMul_Abort (state, ARMul_IRQV); + /*added energy_prof statement by ksh in 2004-11-26 */ + //chy 2005-07-28 for standalone + //ARMul_do_energy(state,instr,pc); + break; + } + +//teawater add for arm2x86 2005.04.26------------------------------------------- +#if 0 +// if (state->pc == 0xc011a868 || state->pc == 0xc011a86c) { + if (state->NumInstrs == 1671574 || state->NumInstrs == 1671573 || state->NumInstrs == 1671572 + || state->NumInstrs == 1671575) { + for (reg_index = 0; reg_index < 16; reg_index ++) { + printf("R%d:%x\t", reg_index, state->Reg[reg_index]); + } + printf("\n"); + } +#endif + if (state->tea_pc) { + int i; + + if (state->tea_reg_fd) { + fprintf (state->tea_reg_fd, "\n"); + for (i = 0; i < 15; i++) { + fprintf (state->tea_reg_fd, "%x,", + state->Reg[i]); + } + fprintf (state->tea_reg_fd, "%x,", pc); + state->Cpsr = ARMul_GetCPSR (state); + fprintf (state->tea_reg_fd, "%x\n", + state->Cpsr); + } else { + printf ("\n"); + for (i = 0; i < 15; i++) { + printf ("%x,", state->Reg[i]); + } + printf ("%x,", pc); + state->Cpsr = ARMul_GetCPSR (state); + printf ("%x\n", state->Cpsr); + } + } +//AJ2D-------------------------------------------------------------------------- + + /*if (state->CallDebug > 0) { + instr = ARMul_Debug (state, pc, instr); + if (state->Emulate < ONCE) { + state->NextInstr = RESUME; + break; + } + if (state->Debug) { + fprintf (stderr, + "sim: At %08lx Instr %08lx Mode %02lx\n", + pc, instr, state->Mode); + (void) fgetc (stdin); + } + } + else*/ + if (state->Emulate < ONCE) { + state->NextInstr = RESUME; + break; + } + //io_do_cycle (state); + state->NumInstrs++; +#if 0 + if (state->NumInstrs % 10000000 == 0) { + printf("10 MIPS instr have been executed\n"); + } +#endif + +#ifdef MODET + /* Provide Thumb instruction decoding. If the processor is in Thumb + mode, then we can simply decode the Thumb instruction, and map it + to the corresponding ARM instruction (by directly loading the + instr variable, and letting the normal ARM simulator + execute). There are some caveats to ensure that the correct + pipelined PC value is used when executing Thumb code, and also for + dealing with the BL instruction. */ + if (TFLAG) { + ARMword armOp = 0; + /* Check if in Thumb mode. */ + switch (ARMul_ThumbDecode(state, pc, instr, &armOp)) { + case t_undefined: + /* This is a Thumb instruction. */ + ARMul_UndefInstr (state, instr); + goto donext; + + case t_branch: + /* Already processed. */ + //pc = state->Reg[15] - 2; + //state->pc = state->Reg[15] - 2; //ichfly why do I need that + goto donext; + + case t_decoded: + /* ARM instruction available. */ + //printf("t decode %04lx -> %08lx\n", instr & 0xffff, armOp); + + if (armOp == 0xDEADC0DE) { + XDSERROR("Failed to decode thumb opcode %04X at %08X", instr, pc); + } + + instr = armOp; + + /* So continue instruction decoding. */ + break; + default: + break; + } + } +#endif + /* Check the condition codes. */ + if ((temp = TOPBITS (28)) == AL) { + /* Vile deed in the need for speed. */ + goto mainswitch; + } + + /* Check the condition code. */ + switch ((int) TOPBITS (28)) { + case AL: + temp = TRUE; + break; + case NV: + + /* shenoubang add for armv7 instr dmb 2012-3-11 */ + if (state->is_v7) { + if ((instr & 0x0fffff00) == 0x057ff000) { + switch((instr >> 4) & 0xf) { + case 4: /* dsb */ + case 5: /* dmb */ + case 6: /* isb */ + // TODO: do no implemented thes instr + goto donext; + } + } + } + /* dyf add for armv6 instruct CPS 2010.9.17 */ + if (state->is_v6) { + /* clrex do nothing here temporary */ + if (instr == 0xf57ff01f) { + //printf("clrex \n"); +#if 0 + int i; + for(i = 0; i < 128; i++) { + state->exclusive_tag_array[i] = 0xffffffff; + } +#endif + /* shenoubang 2012-3-14 refer the dyncom_interpreter */ + state->exclusive_tag_array[0] = 0xFFFFFFFF; + state->exclusive_access_state = 0; + goto donext; + } + + if (BITS(20, 27) == 0x10) { + if (BIT(19)) { + if (BIT(8)) { + if (BIT(18)) + state->Cpsr |= 1<<8; + else + state->Cpsr &= ~(1<<8); + } + if (BIT(7)) { + if (BIT(18)) + state->Cpsr |= 1<<7; + else + state->Cpsr &= ~(1<<7); + ASSIGNINT (state->Cpsr & INTBITS); + } + if (BIT(6)) { + if (BIT(18)) + state->Cpsr |= 1<<6; + else + state->Cpsr &= ~(1<<6); + ASSIGNINT (state->Cpsr & INTBITS); + } + } + if (BIT(17)) { + state->Cpsr |= BITS(0, 4); + printf("skyeye test state->Mode\n"); + if (state->Mode != (state->Cpsr & MODEBITS)) { + state->Mode = ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS); + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + } + } + goto donext; + } + } + if (state->is_v5) { + if (BITS (25, 27) == 5) { /* BLX(1) */ + ARMword dest; + + state->Reg[14] = pc + 4; + + /* Force entry into Thumb mode. */ + dest = pc + 8 + 1; + if (BIT (23)) + dest += (NEGBRANCH + + (BIT (24) << 1)); + else + dest += POSBRANCH + + (BIT (24) << 1); + + WriteR15Branch (state, dest); + goto donext; + } else if ((instr & 0xFC70F000) == 0xF450F000) { + /* The PLD instruction. Ignored. */ + goto donext; + } else if (((instr & 0xfe500f00) == 0xfc100100) + || ((instr & 0xfe500f00) == + 0xfc000100)) { + /* wldrw and wstrw are unconditional. */ + goto mainswitch; + } else { + /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */ + ARMul_UndefInstr (state, instr); + } + } + temp = FALSE; + break; + case EQ: + temp = ZFLAG; + break; + case NE: + temp = !ZFLAG; + break; + case VS: + temp = VFLAG; + break; + case VC: + temp = !VFLAG; + break; + case MI: + temp = NFLAG; + break; + case PL: + temp = !NFLAG; + break; + case CS: + temp = CFLAG; + break; + case CC: + temp = !CFLAG; + break; + case HI: + temp = (CFLAG && !ZFLAG); + break; + case LS: + temp = (!CFLAG || ZFLAG); + break; + case GE: + temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); + break; + case LT: + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); + break; + case GT: + temp = ((!NFLAG && !VFLAG && !ZFLAG) + || (NFLAG && VFLAG && !ZFLAG)); + break; + case LE: + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) + || ZFLAG; + break; + } /* cc check */ + +//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... + + /* Actual execution of instructions begins here. */ + /* If the condition codes don't match, stop here. */ + if (temp) { +mainswitch: + + /* shenoubang sbfx and ubfx instr 2012-3-16 */ + if (state->is_v6) { + unsigned int m, lsb, width, Rd, Rn, data; + Rd = Rn = lsb = width = data = m = 0; + + //printf("helloworld\n"); + if ((((int) BITS (21, 27)) == 0x3f) && (((int) BITS (4, 6)) == 0x5)) { + m = (unsigned)BITS(7, 11); + width = (unsigned)BITS(16, 20); + Rd = (unsigned)BITS(12, 15); + Rn = (unsigned)BITS(0, 3); + if ((Rd == 15) || (Rn == 15)) { + ARMul_UndefInstr (state, instr); + } else if ((m + width) < 32) { + data = state->Reg[Rn]; + state->Reg[Rd] ^= state->Reg[Rd]; + state->Reg[Rd] = ((ARMword)(data << (31 -(m + width))) >> ((31 - (m + width)) + (m))); + //SKYEYE_LOG_IN_CLR(RED, "UBFX: In %s, line = %d, Reg_src[%d] = 0x%x, Reg_d[%d] = 0x%x, m = %d, width = %d, Rd = %d, Rn = %d\n", + // __FUNCTION__, __LINE__, Rn, data, Rd, state->Reg[Rd], m, width + 1, Rd, Rn); + goto donext; + } + } // ubfx instr + else if ((((int) BITS (21, 27)) == 0x3d) && (((int) BITS (4, 6)) == 0x5)) { + int tmp = 0; + Rd = BITS(12, 15); + Rn = BITS(0, 3); + lsb = BITS(7, 11); + width = BITS(16, 20); + if ((Rd == 15) || (Rn == 15)) { + ARMul_UndefInstr (state, instr); + } else if ((lsb + width) < 32) { + state->Reg[Rd] ^= state->Reg[Rd]; + data = state->Reg[Rn]; + tmp = (data << (32 - (lsb + width + 1))); + state->Reg[Rd] = (tmp >> (32 - (lsb + width + 1))); + //SKYEYE_LOG_IN_CLR(RED, "sbfx: In %s, line = %d, pc = 0x%x, instr = 0x%x,Rd = 0x%x, Rn = 0x%x, lsb = %d, width = %d, Rs[%d] = 0x%x, Rd[%d] = 0x%x\n", + // __func__, __LINE__, pc, instr, Rd, Rn, lsb, width + 1, Rn, state->Reg[Rn], Rd, state->Reg[Rd]); + goto donext; + } + } // sbfx instr + else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) { + //(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) + unsigned msb ,tmp_rn, tmp_rd, dst; + tmp_rd = tmp_rn = dst = 0; + Rd = BITS(12, 15); + Rn = BITS(0, 3); + lsb = BITS(7, 11); + msb = BITS(16, 20); //-V519 + if ((Rd == 15)) { + ARMul_UndefInstr (state, instr); + } else if ((Rn == 15)) { + data = state->Reg[Rd]; + tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); + dst = ((data >> msb) << (msb - lsb)); + dst = (dst << lsb) | tmp_rd; + goto donext; + } // bfc instr + else if (((msb >= lsb) && (msb < 32))) { + data = state->Reg[Rn]; + tmp_rn = ((ARMword)(data << (31 - (msb - lsb))) >> (31 - (msb - lsb))); + data = state->Reg[Rd]; + tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); + dst = ((data >> msb) << (msb - lsb)) | tmp_rn; + dst = (dst << lsb) | tmp_rd; + goto donext; + } // bfi instr + } + } + + switch ((int) BITS (20, 27)) { + /* Data Processing Register RHS Instructions. */ + + case 0x00: /* AND reg and MUL */ +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, no write-back, down, post indexed. */ + SHDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 7) == 9) { + /* MUL */ + rhs = state->Reg[MULRHSReg]; + //if (MULLHSReg == MULDESTReg) { + if(0) { /* For armv6, the restriction is removed */ + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = 0; + } else if (MULDESTReg != 15) + state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs; + else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; + dest++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } else { + /* AND reg. */ + rhs = DPRegRHS; + dest = LHS & rhs; + WRITEDEST (dest); + } + break; + + case 0x01: /* ANDS reg and MULS */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to rest of decoding. */ +#endif + if (BITS (4, 7) == 9) { + /* MULS */ + rhs = state->Reg[MULRHSReg]; + + //if (MULLHSReg == MULDESTReg) { + if(0) { + printf("Something in %d line\n", __LINE__); + UNDEF_WARNING; + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = 0; + CLEARN; + SETZ; + } else if (MULDESTReg != 15) { + dest = state->Reg[MULLHSReg] * rhs; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; + dest++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } else { + /* ANDS reg. */ + rhs = DPSRegRHS; + dest = LHS & rhs; + WRITESDEST (dest); + } + break; + + case 0x02: /* EOR reg and MLA */ +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, write-back, down, post indexed. */ + SHDOWNWB (); + break; + } +#endif + if (BITS (4, 7) == 9) { /* MLA */ + rhs = state->Reg[MULRHSReg]; +#if 0 + if (MULLHSReg == MULDESTReg) { + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = state->Reg[MULACCReg]; + } else if (MULDESTReg != 15) { +#endif + if (MULDESTReg != 15) { + state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; + } else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; + dest++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } else { + rhs = DPRegRHS; + dest = LHS ^ rhs; + WRITEDEST (dest); + } + break; + + case 0x03: /* EORS reg and MLAS */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, down, post-indexed. */ + LHPOSTDOWN (); + /* Fall through to rest of the decoding. */ +#endif + if (BITS (4, 7) == 9) { + /* MLAS */ + rhs = state->Reg[MULRHSReg]; + //if (MULLHSReg == MULDESTReg) { + if (0) { + UNDEF_MULDestEQOp1; + dest = state->Reg[MULACCReg]; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } else if (MULDESTReg != 15) { + dest = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; + dest++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } else { + /* EORS Reg. */ + rhs = DPSRegRHS; + dest = LHS ^ rhs; + WRITESDEST (dest); + } + break; + + case 0x04: /* SUB reg */ + // Signifies UMAAL + if (state->is_v6 && BITS(4, 7) == 0x09) { + if (handle_v6_insn(state, instr)) + break; + } + +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, no write-back, down, post indexed. */ + SHDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS - rhs; + WRITEDEST (dest); + break; + + case 0x05: /* SUBS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to the rest of the instruction decoding. */ +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs; + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x06: /* RSB reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, write-back, down, post indexed. */ + SHDOWNWB (); + break; + } +#endif + rhs = DPRegRHS; + dest = rhs - LHS; + WRITEDEST (dest); + break; + + case 0x07: /* RSBS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to remainder of instruction decoding. */ +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = rhs - lhs; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x08: /* ADD reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, no write-back, up, post indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif +#ifdef MODET + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32 = 64 */ + ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS + rhs; + WRITEDEST (dest); + break; + + case 0x09: /* ADDS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ +#endif +#ifdef MODET + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LSCC), 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0a: /* ADC reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, write-back, up, post-indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS + rhs + CFLAG; + WRITEDEST (dest); + break; + + case 0x0b: /* ADCS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LSCC), 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs + CFLAG; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0c: /* SBC reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, no write-back, up post indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS - rhs - !CFLAG; + WRITEDEST (dest); + break; + + case 0x0d: /* SBCS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, up, post indexed. */ + LHPOSTUP (); + + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LSCC), 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs - !CFLAG; + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0e: /* RSC reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, write-back, up, post indexed. */ + SHUPWB (); + break; + } + + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = rhs - LHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x0f: /* RSCS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ + + if (BITS (4, 7) == 0x9) { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LSCC), 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = rhs - lhs - !CFLAG; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x10: /* TST reg and MRS CPSR and SWP word. */ + if (state->is_v5e) { + if (BIT (4) == 0 && BIT (7) == 1) { + /* ElSegundo SMLAxy insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (8, 11)]; + ARMword Rn = state->Reg[BITS (12, 15)]; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + op2 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + if (op2 & 0x8000) + op2 -= 65536; + op1 *= op2; + //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn); + if (AddOverflow(op1, Rn, op1 + Rn)) + SETQ; + state->Reg[BITS (16, 19)] = op1 + Rn; + break; + } + + if (BITS (4, 11) == 5) { + /* ElSegundo QADD insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword result = op1 + op2; + if (AddOverflow(op1, op2, result)) { + result = POS (result) ? 0x80000000 : 0x7fffffff; + SETQ; + } + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, no write-back, down, pre indexed. */ + SHPREDOWN (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 11) == 9) { + /* SWP */ + UNDEF_SWPPC; + temp = LHS; + BUSUSEDINCPCS; +#ifndef MODE32 + if (VECTORACCESS (temp) || ADDREXCEPT (temp)) { + INTERNALABORT (temp); + (void) ARMul_LoadWordN (state, temp); + (void) ARMul_LoadWordN (state, temp); + } else +#endif + dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]); + if (temp & 3) + DEST = ARMul_Align (state, temp, dest); + else + DEST = dest; + if (state->abortSig || state->Aborted) + TAKEABORT; + } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */ + UNDEF_MRSPC; + DEST = ARMul_GetCPSR(state); + } else { + UNDEF_Test; + } + break; + + case 0x11: /* TSTP reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, down, pre indexed. */ + LHPREDOWN (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) { + /* TSTP reg */ +#ifdef MODE32 + //chy 2006-02-15 if in user mode, can not set cpsr 0:23 + //from p165 of ARMARM book + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS & rhs; + SETR15PSR (temp); +#endif + } else { + /* TST reg */ + rhs = DPSRegRHS; + dest = LHS & rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */ + + if (state->is_v5) { + if (BITS (4, 7) == 3) { + /* BLX(2) */ + ARMword temp; + + if (TFLAG) + temp = (pc + 2) | 1; + else + temp = pc + 4; + + WriteR15Branch (state, state->Reg[RHSReg]); + state->Reg[14] = temp; + break; + } + } + + if (state->is_v5e) { + if (BIT (4) == 0 && BIT (7) == 1 && (BIT (5) == 0 || BITS (12, 15) == 0)) { + /* ElSegundo SMLAWy/SMULWy insn. */ + unsigned long long op1 = state->Reg[BITS (0, 3)]; + unsigned long long op2 = state->Reg[BITS (8, 11)]; + unsigned long long result; + + if (BIT (6)) + op2 >>= 16; + if (op1 & 0x80000000) + op1 -= 1ULL << 32; + op2 &= 0xFFFF; + if (op2 & 0x8000) + op2 -= 65536; + result = (op1 * op2) >> 16; + + if (BIT (5) == 0) { + ARMword Rn = state->Reg[BITS(12, 15)]; + + if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn))) + SETQ; + result += Rn; + } + state->Reg[BITS (16, 19)] = (ARMword)result; + break; + } + + if (BITS (4, 11) == 5) { + /* ElSegundo QSUB insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword result = op1 - op2; + + if (SubOverflow + (op1, op2, result)) { + result = POS (result) ? 0x80000000 : 0x7fffffff; + SETQ; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, write-back, down, pre indexed. */ + SHPREDOWNWB (); + break; + } + if (BITS (4, 27) == 0x12FFF1) { + /* BX */ + WriteR15Branch (state, state->Reg[RHSReg]); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + if (state->is_v5) { + if (BITS (4, 7) == 0x7) { + //ARMword value; + //extern int SWI_vector_installed; + + /* Hardware is allowed to optionally override this + instruction and treat it as a breakpoint. Since + this is a simulator not hardware, we take the position + that if a SWI vector was not installed, then an Abort + vector was probably not installed either, and so + normally this instruction would be ignored, even if an + Abort is generated. This is a bad thing, since GDB + uses this instruction for its breakpoints (at least in + Thumb mode it does). So intercept the instruction here + and generate a breakpoint SWI instead. */ + /* Force the next instruction to be refetched. */ + state->NextInstr = RESUME; + break; + } + } + if (DESTReg == 15) { + /* MSR reg to CPSR. */ + UNDEF_MSRPC; + temp = DPRegRHS; +#ifdef MODET + /* Don't allow TBIT to be set by MSR. */ + temp &= ~TBIT; +#endif + ARMul_FixCPSR (state, instr, temp); + } else + UNDEF_Test; + + break; + + case 0x13: /* TEQP reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, down, pre indexed. */ + LHPREDOWNWB (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) { + /* TEQP reg */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS ^ rhs; + SETR15PSR (temp); +#endif + } else { + /* TEQ Reg. */ + rhs = DPSRegRHS; + dest = LHS ^ rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x14: /* CMP reg and MRS SPSR and SWP byte. */ + if (state->is_v5e) { + if (BIT (4) == 0 && BIT (7) == 1) { + /* ElSegundo SMLALxy insn. */ + unsigned long long op1 = state->Reg[BITS (0, 3)]; + unsigned long long op2 = state->Reg[BITS (8, 11)]; + unsigned long long dest; + //unsigned long long result; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + op2 &= 0xFFFF; + if (op2 & 0x8000) + op2 -= 65536; + + dest = (unsigned long long) state->Reg[BITS (16, 19)] << 32; + dest |= state->Reg[BITS (12, 15)]; + dest += op1 * op2; + state->Reg[BITS(12, 15)] = (ARMword)dest; + state->Reg[BITS(16, 19)] = (ARMword)(dest >> 32); + break; + } + + if (BITS (4, 11) == 5) { + /* ElSegundo QDADD insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword op2d = op2 + op2; + ARMword result; + + if (AddOverflow + (op2, op2, op2d)) { + SETQ; + op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; + } + + result = op1 + op2d; + if (AddOverflow(op1, op2d, result)) { + SETQ; + result = POS (result) ? 0x80000000 : 0x7fffffff; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, no write-back, down, pre indexed. */ + SHPREDOWN (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 11) == 9) { + /* SWP */ + UNDEF_SWPPC; + temp = LHS; + BUSUSEDINCPCS; +#ifndef MODE32 + if (VECTORACCESS (temp) || ADDREXCEPT (temp)) { + INTERNALABORT (temp); + (void) ARMul_LoadByte (state, temp); + (void) ARMul_LoadByte (state, temp); + } else +#endif + DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]); + if (state->abortSig || state->Aborted) + TAKEABORT; + } else if ((BITS (0, 11) == 0) + && (LHSReg == 15)) { + /* MRS SPSR */ + UNDEF_MRSPC; + DEST = GETSPSR (state->Bank); + } else + UNDEF_Test; + + break; + + case 0x15: /* CMPP reg. */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, down, pre indexed. */ + LHPREDOWN (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) { + /* CMPP reg. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS - rhs; + SETR15PSR (temp); +#endif + } else { + /* CMP reg. */ + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs; + ARMul_NegZero (state, dest); + if ((lhs >= rhs) + || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + } + break; + + case 0x16: /* CMN reg and MSR reg to SPSR */ + if (state->is_v5e) { + if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0) { + /* ElSegundo SMULxy insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (8, 11)]; + ARMword Rn = state->Reg[BITS (12, 15)]; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + op2 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + if (op2 & 0x8000) + op2 -= 65536; + + state->Reg[BITS (16, 19)] = op1 * op2; + break; + } + + if (BITS (4, 11) == 5) { + /* ElSegundo QDSUB insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword op2d = op2 + op2; + ARMword result; + + if (AddOverflow(op2, op2, op2d)) { + SETQ; + op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; + } + + result = op1 - op2d; + if (SubOverflow(op1, op2d, result)) { + SETQ; + result = POS (result) ? 0x80000000 : 0x7fffffff; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } + + if (state->is_v5) { + if (BITS (4, 11) == 0xF1 + && BITS (16, 19) == 0xF) { + /* ARM5 CLZ insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + int result = 32; + + if (op1) + for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1) + result++; + state->Reg[BITS (12, 15)] = result; + break; + } + } + +#ifdef MODET + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, write-back, down, pre indexed. */ + SHPREDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + if (DESTReg == 15) { + /* MSR */ + UNDEF_MSRPC; + /*ARMul_FixSPSR (state, instr, + DPRegRHS);*/ + } else { + UNDEF_Test; + } + break; + + case 0x17: /* CMNP reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, down, pre indexed. */ + LHPREDOWNWB (); + /* Continue with remaining instruction decoding. */ +#endif + if (DESTReg == 15) { +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS + rhs; + SETR15PSR (temp); +#endif + break; + } else { + /* CMN reg. */ + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + } + break; + + case 0x18: /* ORR reg */ +#ifdef MODET + /* dyf add armv6 instr strex 2010.9.17 */ + if (state->is_v6) { + if (BITS (4, 7) == 0x9) + if (handle_v6_insn (state, instr)) + break; + } + + if (BITS (4, 11) == 0xB) { + /* STRH register offset, no write-back, up, pre indexed. */ + SHPREUP (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS | rhs; + WRITEDEST (dest); + break; + + case 0x19: /* ORRS reg */ +#ifdef MODET + /* dyf add armv6 instr ldrex */ + if (state->is_v6) { + if (BITS (4, 7) == 0x9) { + if (handle_v6_insn (state, instr)) + break; + } + } + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, up, pre indexed. */ + LHPREUP (); + /* Continue with remaining instruction decoding. */ +#endif + rhs = DPSRegRHS; + dest = LHS | rhs; + WRITESDEST (dest); + break; + + case 0x1a: /* MOV reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) { + /* STRH register offset, write-back, up, pre indexed. */ + SHPREUPWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } + if (BITS(4, 11) == 0xF9) { //strexd + u32 l = LHSReg; + + bool enter = false; + + if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr)&& + state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4)) + enter = true; + + //todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html + + if (enter) { + ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]); + ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]); + state->Reg[DESTReg] = 0; + } else { + state->Reg[DESTReg] = 1; + } + + break; + } +#endif + dest = DPRegRHS; + WRITEDEST (dest); + break; + + case 0x1B: /* MOVS reg */ +#ifdef MODET + /* ldrexd ichfly */ + if (BITS(0, 11) == 0xF9F) { //strexd + lhs = LHS; + + state->currentexaddr = lhs; + state->currentexval = (u32)ARMul_ReadWord(state, lhs); + state->currentexvald = (u32)ARMul_ReadWord(state, lhs + 4); + + state->Reg[DESTReg] = ARMul_LoadWordN(state, lhs); + state->Reg[DESTReg] = ARMul_LoadWordN(state, lhs + 4); + break; + } + + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, up, pre indexed. */ + LHPREUPWB (); + /* Continue with remaining instruction decoding. */ + +#endif + dest = DPSRegRHS; + WRITESDEST (dest); + break; + + case 0x1c: /* BIC reg */ +#ifdef MODET + /* dyf add for STREXB */ + if (state->is_v6) { + if (BITS (4, 7) == 0x9) { + if (handle_v6_insn (state, instr)) + break; + } + } + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, no write-back, up, pre indexed. */ + SHPREUP (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } else if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS & ~rhs; + WRITEDEST (dest); + break; + + case 0x1d: /* BICS reg */ +#ifdef MODET + /* ladsh P=1 U=1 W=0 L=1 S=1 H=1 */ + if (BITS(4, 7) == 0xF) { + temp = LHS + GetLS7RHS (state, instr); + LoadHalfWord (state, instr, temp, LSIGNED); + break; + } + if (BITS (4, 7) == 0xb) { + /* LDRH immediate offset, no write-back, up, pre indexed. */ + temp = LHS + GetLS7RHS (state, instr); + LoadHalfWord (state, instr, temp, LUNSIGNED); + break; + } + if (BITS (4, 7) == 0xd) { + // alex-ykl fix: 2011-07-20 missing ldrsb instruction + temp = LHS + GetLS7RHS (state, instr); + LoadByte (state, instr, temp, LSIGNED); + break; + } + + /* Continue with instruction decoding. */ + /*if ((BITS (4, 7) & 0x9) == 0x9) */ + if ((BITS (4, 7)) == 0x9) { + /* ldrexb */ + if (state->is_v6) { + if (handle_v6_insn (state, instr)) + break; + } + /* LDR immediate offset, no write-back, up, pre indexed. */ + LHPREUP (); + } + +#endif + rhs = DPSRegRHS; + dest = LHS & ~rhs; + WRITESDEST (dest); + break; + + case 0x1e: /* MVN reg */ +#ifdef MODET + if ((instr & 0x00000FF0) == 0x00000F90) { //if ((instr & 0x0FF00FF0) == 0x01e00f90) { //todo make that better ichfly + /* strexh ichfly */ + u32 l = LHSReg; + u32 r = RHSReg; + lhs = LHS; + + bool enter = false; + + if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true; + + //StoreWord(state, lhs, RHS) + if (state->Aborted) { + TAKEABORT; + } + if (enter) { + ARMul_StoreHalfWord(state, lhs, RHS); + state->Reg[DESTReg] = 0; + } else { + state->Reg[DESTReg] = 1; + } + break; + } + if (BITS (4, 7) == 0xB) { + /* STRH immediate offset, write-back, up, pre indexed. */ + SHPREUPWB (); + break; + } + if (BITS (4, 7) == 0xD) { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) { + Handle_Store_Double (state, instr); + break; + } +#endif + dest = ~DPRegRHS; + WRITEDEST (dest); + break; + + case 0x1f: /* MVNS reg */ +#ifdef MODET + + if ((instr & 0x00000FF0) == 0x00000F90) { //(instr & 0x0FF00FF0) == 0x01f00f90)//if ((instr & 0x0FF00FF0) == 0x01f00f90) { + /* ldrexh ichfly */ + lhs = LHS; + + state->currentexaddr = lhs; + state->currentexval = (u32)ARMul_LoadHalfWord(state, lhs); + + LoadHalfWord(state, instr, lhs,0); + break; + } + + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, up, pre indexed. */ + LHPREUPWB (); + /* Continue instruction decoding. */ +#endif + dest = ~DPSRegRHS; + WRITESDEST (dest); + break; + + /* Data Processing Immediate RHS Instructions. */ + + case 0x20: /* AND immed */ + dest = LHS & DPImmRHS; + WRITEDEST (dest); + break; + + case 0x21: /* ANDS immed */ + DPSImmRHS; + dest = LHS & rhs; + WRITESDEST (dest); + break; + + case 0x22: /* EOR immed */ + dest = LHS ^ DPImmRHS; + WRITEDEST (dest); + break; + + case 0x23: /* EORS immed */ + DPSImmRHS; + dest = LHS ^ rhs; + WRITESDEST (dest); + break; + + case 0x24: /* SUB immed */ + dest = LHS - DPImmRHS; + WRITEDEST (dest); + break; + + case 0x25: /* SUBS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs; + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x26: /* RSB immed */ + dest = DPImmRHS - LHS; + WRITEDEST (dest); + break; + + case 0x27: /* RSBS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = rhs - lhs; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x28: /* ADD immed */ + dest = LHS + DPImmRHS; + WRITEDEST (dest); + break; + + case 0x29: /* ADDS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2a: /* ADC immed */ + dest = LHS + DPImmRHS + CFLAG; + WRITEDEST (dest); + break; + + case 0x2b: /* ADCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs + CFLAG; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2c: /* SBC immed */ + dest = LHS - DPImmRHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x2d: /* SBCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs - !CFLAG; + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2e: /* RSC immed */ + dest = DPImmRHS - LHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x2f: /* RSCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = rhs - lhs - !CFLAG; + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } else { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x30: /* TST immed */ + /* shenoubang 2012-3-14*/ + if (state->is_v6) { /* movw, ARMV6, ARMv7 */ + dest ^= dest; + dest = BITS(16, 19); + dest = ((dest<<12) | BITS(0, 11)); + WRITEDEST(dest); + break; + } else { + UNDEF_Test; + break; + } + + case 0x31: /* TSTP immed */ + if (DESTReg == 15) { + /* TSTP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS & DPImmRHS; + SETR15PSR (temp); +#endif + } else { + /* TST immed. */ + DPSImmRHS; + dest = LHS & rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x32: /* TEQ immed and MSR immed to CPSR */ + if (DESTReg == 15) + /* MSR immed to CPSR. */ + ARMul_FixCPSR (state, instr, + DPImmRHS); + else + UNDEF_Test; + break; + + case 0x33: /* TEQP immed */ + if (DESTReg == 15) { + /* TEQP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS ^ DPImmRHS; + SETR15PSR (temp); +#endif + } else { + DPSImmRHS; /* TEQ immed */ + dest = LHS ^ rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x34: /* CMP immed */ + UNDEF_Test; + break; + + case 0x35: /* CMPP immed */ + if (DESTReg == 15) { + /* CMPP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS - DPImmRHS; + SETR15PSR (temp); +#endif + break; + } else { + /* CMP immed. */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs; + ARMul_NegZero (state, dest); + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } else { + CLEARC; + CLEARV; + } + } + break; + + case 0x36: /* CMN immed and MSR immed to SPSR */ + //if (DESTReg == 15) + /*ARMul0_FixSPSR (state, instr, + DPImmRHS);*/ + //else + UNDEF_Test; + break; + + case 0x37: /* CMNP immed. */ + if (DESTReg == 15) { + /* CMNP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS + DPImmRHS; + SETR15PSR (temp); +#endif + break; + } else { + /* CMN immed. */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } else { + CLEARN; + CLEARC; + CLEARV; + } + } + break; + + case 0x38: /* ORR immed. */ + dest = LHS | DPImmRHS; + WRITEDEST (dest); + break; + + case 0x39: /* ORRS immed. */ + DPSImmRHS; + dest = LHS | rhs; + WRITESDEST (dest); + break; + + case 0x3a: /* MOV immed. */ + dest = DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3b: /* MOVS immed. */ + DPSImmRHS; + WRITESDEST (rhs); + break; + + case 0x3c: /* BIC immed. */ + dest = LHS & ~DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3d: /* BICS immed. */ + DPSImmRHS; + dest = LHS & ~rhs; + WRITESDEST (dest); + break; + + case 0x3e: /* MVN immed. */ + dest = ~DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3f: /* MVNS immed. */ + DPSImmRHS; + WRITESDEST (~rhs); + break; + + /* Single Data Transfer Immediate RHS Instructions. */ + + case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (LoadWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + temp = lhs - LSImmRHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs - LSImmRHS; + break; + + case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (LoadWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ + (void) StoreWord (state, instr, LHS - LSImmRHS); + break; + + case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */ + (void) LoadWord (state, instr, LHS - LSImmRHS); + break; + + case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */ + (void) StoreByte (state, instr, LHS - LSImmRHS); + break; + + case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */ + (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED); + break; + + case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */ + (void) StoreWord (state, instr, LHS + LSImmRHS); + break; + + case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */ + (void) LoadWord (state, instr, LHS + LSImmRHS); + break; + + case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */ + (void) StoreByte (state, instr, LHS + LSImmRHS); + break; + + case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */ + (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED); + break; + + case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + /* Single Data Transfer Register RHS Instructions. */ + + case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + break; + + case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + break; + + case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + break; + + case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + break; + + case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ + if ((instr & 0x70) == 0x10) { //pkhbt + u8 idest = BITS(12, 15); + u8 rfis = BITS(16, 19); + u8 rlast = BITS(0, 3); + u8 ishi = BITS(7,11); + state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000); + break; + } else if ((instr & 0x70) == 0x50) { //pkhtb + u8 rd_idx = BITS(12, 15); + u8 rn_idx = BITS(16, 19); + u8 rm_idx = BITS(0, 3); + u8 imm5 = BITS(7, 11) ? BITS(7, 11) : 31; + state->Reg[rd_idx] = ((static_cast(state->Reg[rm_idx]) >> imm5) & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000); + break; + } else if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + break; + + case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + break; + + case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + break; + + case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + break; + + case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ +#if 0 + if (state->is_v6) { + int Rm = 0; + /* utxb */ + if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) { + Rm = (RHS >> (8 * BITS(10, 11))) & 0xff; + DEST = Rm; + } + } +#endif + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreWord (state, instr, LHS - LSRegRHS); + break; + + case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadWord (state, instr, LHS - LSRegRHS); + break; + + case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreByte (state, instr, LHS - LSRegRHS); + break; + + case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED); + break; + + case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreWord (state, instr, LHS + LSRegRHS); + break; + + case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadWord (state, instr, LHS + LSRegRHS); + break; + + case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { +#ifdef MODE32 + if (state->is_v6 && handle_v6_insn (state, instr)) + break; +#endif + + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreByte (state, instr, LHS + LSRegRHS); + break; + + case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED); + break; + + case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) { + //LOG_DEBUG(Core_ARM11, "got unhandled special breakpoint"); + return 1; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + /* Multiple Data Transfer Instructions. */ + + case 0x80: /* Store, No WriteBack, Post Dec. */ + STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x81: /* Load, No WriteBack, Post Dec. */ + LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x82: /* Store, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + STOREMULT (instr, temp + 4L, temp); + break; + + case 0x83: /* Load, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + LOADMULT (instr, temp + 4L, temp); + break; + + case 0x84: /* Store, Flags, No WriteBack, Post Dec. */ + STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x85: /* Load, Flags, No WriteBack, Post Dec. */ + LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x86: /* Store, Flags, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + STORESMULT (instr, temp + 4L, temp); + break; + + case 0x87: /* Load, Flags, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + LOADSMULT (instr, temp + 4L, temp); + break; + + case 0x88: /* Store, No WriteBack, Post Inc. */ + STOREMULT (instr, LSBase, 0L); + break; + + case 0x89: /* Load, No WriteBack, Post Inc. */ + LOADMULT (instr, LSBase, 0L); + break; + + case 0x8a: /* Store, WriteBack, Post Inc. */ + temp = LSBase; + STOREMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8b: /* Load, WriteBack, Post Inc. */ + temp = LSBase; + LOADMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */ + STORESMULT (instr, LSBase, 0L); + break; + + case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */ + LOADSMULT (instr, LSBase, 0L); + break; + + case 0x8e: /* Store, Flags, WriteBack, Post Inc. */ + temp = LSBase; + STORESMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8f: /* Load, Flags, WriteBack, Post Inc. */ + temp = LSBase; + LOADSMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x90: /* Store, No WriteBack, Pre Dec. */ + STOREMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x91: /* Load, No WriteBack, Pre Dec. */ + LOADMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x92: /* Store, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + STOREMULT (instr, temp, temp); + break; + + case 0x93: /* Load, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + LOADMULT (instr, temp, temp); + break; + + case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */ + STORESMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */ + LOADSMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x96: /* Store, Flags, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + STORESMULT (instr, temp, temp); + break; + + case 0x97: /* Load, Flags, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + LOADSMULT (instr, temp, temp); + break; + + case 0x98: /* Store, No WriteBack, Pre Inc. */ + STOREMULT (instr, LSBase + 4L, 0L); + break; + + case 0x99: /* Load, No WriteBack, Pre Inc. */ + LOADMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9a: /* Store, WriteBack, Pre Inc. */ + temp = LSBase; + STOREMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9b: /* Load, WriteBack, Pre Inc. */ + temp = LSBase; + LOADMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */ + STORESMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */ + LOADSMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */ + temp = LSBase; + STORESMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */ + temp = LSBase; + LOADSMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + /* Branch forward. */ + case 0xa0: + case 0xa1: + case 0xa2: + case 0xa3: + case 0xa4: + case 0xa5: + case 0xa6: + case 0xa7: + state->Reg[15] = pc + 8 + POSBRANCH; + FLUSHPIPE; + break; + + /* Branch backward. */ + case 0xa8: + case 0xa9: + case 0xaa: + case 0xab: + case 0xac: + case 0xad: + case 0xae: + case 0xaf: + state->Reg[15] = pc + 8 + NEGBRANCH; + FLUSHPIPE; + break; + + /* Branch and Link forward. */ + case 0xb0: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + + /* Put PC into Link. */ +#ifdef MODE32 + state->Reg[14] = pc + 4; +#else + state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; +#endif + state->Reg[15] = pc + 8 + POSBRANCH; + FLUSHPIPE; + +#ifdef callstacker + memset(a, 0, 256); + aufloeser(a, state->Reg[15]); + printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); +#endif + + break; + + /* Branch and Link backward. */ + case 0xb8: + case 0xb9: + case 0xba: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + case 0xbf: + /* Put PC into Link. */ +#ifdef MODE32 + state->Reg[14] = pc + 4; +#else + state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; +#endif + state->Reg[15] = pc + 8 + NEGBRANCH; + FLUSHPIPE; + +#ifdef callstacker + memset(a, 0, 256); + aufloeser(a, state->Reg[15]); + printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); +#endif + + break; + + /* Co-Processor Data Transfers. */ + case 0xc4: + if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0 + state->ExtReg[BITS(0, 3) << 1] = state->Reg[BITS(12, 15)]; + state->ExtReg[(BITS(0, 3) << 1) + 1] = state->Reg[BITS(16, 20)]; + break; + } else if (state->is_v5) { + /* Reading from R15 is UNPREDICTABLE. */ + if (BITS (12, 15) == 15 || BITS (16, 19) == 15) + ARMul_UndefInstr (state, instr); + /* Is access to coprocessor 0 allowed ? */ + else if (!CP_ACCESS_ALLOWED(state, CPNum)) + ARMul_UndefInstr (state, instr); + else { + /* MCRR, ARMv5TE and up */ + ARMul_MCRR (state, instr, DEST, state->Reg[LHSReg]); + break; + } + } + /* Drop through. */ + + case 0xc0: /* Store , No WriteBack , Post Dec. */ + ARMul_STC (state, instr, LHS); + break; + + case 0xc5: + if ((instr & 0x00000FF0) == 0xB10) { //vmov BIT(12-15), BIT(16-20), BIT(0-3) vmov r0, r0, d0 + state->Reg[BITS(12, 15)] = state->ExtReg[BITS(0, 3) << 1]; + state->Reg[BITS(16, 19)] = state->ExtReg[(BITS(0, 3) << 1) + 1]; + break; + } else if (state->is_v5) { + /* Writes to R15 are UNPREDICATABLE. */ + if (DESTReg == 15 || LHSReg == 15) + ARMul_UndefInstr (state, instr); + /* Is access to the coprocessor allowed ? */ + else if (!CP_ACCESS_ALLOWED(state, CPNum)) { + ARMul_UndefInstr(state, instr); + } else { + /* MRRC, ARMv5TE and up */ + ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg])); + break; + } + } + /* Drop through. */ + + case 0xc1: /* Load , No WriteBack , Post Dec. */ + ARMul_LDC (state, instr, LHS); + break; + + case 0xc2: + case 0xc6: /* Store , WriteBack , Post Dec. */ + lhs = LHS; + state->Base = lhs - LSCOff; + ARMul_STC (state, instr, lhs); + break; + + case 0xc3: + case 0xc7: /* Load , WriteBack , Post Dec. */ + lhs = LHS; + state->Base = lhs - LSCOff; + ARMul_LDC (state, instr, lhs); + break; + + case 0xc8: + case 0xcc: /* Store , No WriteBack , Post Inc. */ + ARMul_STC (state, instr, LHS); + break; + + case 0xc9: + case 0xcd: /* Load , No WriteBack , Post Inc. */ + ARMul_LDC (state, instr, LHS); + break; + + case 0xca: + case 0xce: /* Store , WriteBack , Post Inc. */ + lhs = LHS; + state->Base = lhs + LSCOff; + ARMul_STC (state, instr, LHS); + break; + + case 0xcb: + case 0xcf: /* Load , WriteBack , Post Inc. */ + lhs = LHS; + state->Base = lhs + LSCOff; + ARMul_LDC (state, instr, LHS); + break; + + case 0xd0: + case 0xd4: /* Store , No WriteBack , Pre Dec. */ + ARMul_STC (state, instr, LHS - LSCOff); + break; + + case 0xd1: + case 0xd5: /* Load , No WriteBack , Pre Dec. */ + ARMul_LDC (state, instr, LHS - LSCOff); + break; + + case 0xd2: + case 0xd6: /* Store , WriteBack , Pre Dec. */ + lhs = LHS - LSCOff; + state->Base = lhs; + ARMul_STC (state, instr, lhs); + break; + + case 0xd3: + case 0xd7: /* Load , WriteBack , Pre Dec. */ + lhs = LHS - LSCOff; + state->Base = lhs; + ARMul_LDC (state, instr, lhs); + break; + + case 0xd8: + case 0xdc: /* Store , No WriteBack , Pre Inc. */ + ARMul_STC (state, instr, LHS + LSCOff); + break; + + case 0xd9: + case 0xdd: /* Load , No WriteBack , Pre Inc. */ + ARMul_LDC (state, instr, LHS + LSCOff); + break; + + case 0xda: + case 0xde: /* Store , WriteBack , Pre Inc. */ + lhs = LHS + LSCOff; + state->Base = lhs; + ARMul_STC (state, instr, lhs); + break; + + case 0xdb: + case 0xdf: /* Load , WriteBack , Pre Inc. */ + lhs = LHS + LSCOff; + state->Base = lhs; + ARMul_LDC (state, instr, lhs); + break; + + /* Co-Processor Register Transfers (MCR) and Data Ops. */ + + case 0xe2: + /*if (!CP_ACCESS_ALLOWED (state, CPNum)) { + ARMul_UndefInstr (state, instr); + break; + }*/ + + case 0xe0: + case 0xe4: + case 0xe6: + case 0xe8: + case 0xea: + case 0xec: + case 0xee: + if (BIT (4)) { + /* MCR. */ + if (DESTReg == 15) { + UNDEF_MCRPC; +#ifdef MODE32 + ARMul_MCR (state, instr, state->Reg[15] + isize); +#else + ARMul_MCR (state, instr, ECC | ER15INT | EMODE | ((state->Reg[15] + isize) & R15PCBITS)); +#endif + } else + ARMul_MCR (state, instr, DEST); + } else + /* CDP Part 1. */ + ARMul_CDP (state, instr); + break; + + /* Co-Processor Register Transfers (MRC) and Data Ops. */ + case 0xe1: + case 0xe3: + case 0xe5: + case 0xe7: + case 0xe9: + case 0xeb: + case 0xed: + case 0xef: + if (BIT (4)) { + /* MRC */ + temp = ARMul_MRC (state, instr); + if (DESTReg == 15) { + ASSIGNN ((temp & NBIT) != 0); + ASSIGNZ ((temp & ZBIT) != 0); + ASSIGNC ((temp & CBIT) != 0); + ASSIGNV ((temp & VBIT) != 0); + } else + DEST = temp; + } else + /* CDP Part 2. */ + ARMul_CDP (state, instr); + break; + + /* SWI instruction. */ + case 0xf0: + case 0xf1: + case 0xf2: + case 0xf3: + case 0xf4: + case 0xf5: + case 0xf6: + case 0xf7: + case 0xf8: + case 0xf9: + case 0xfa: + case 0xfb: + case 0xfc: + case 0xfd: + case 0xfe: + case 0xff: + //svc_Execute(state, BITS(0, 23)); + ProcessSwi(BITS(0, 7), state->Reg, state->m_currentThread); + + break; + } + } + +#ifdef MODET +donext: +#endif + state->pc = pc; +#if 0 + /* shenoubang */ + instr_sum++; + int i, j; + i = j = 0; + if (instr_sum >= 7388648) { + //if (pc == 0xc0008ab4) { + // printf("instr_sum: %d\n", instr_sum); + // start_kernel : 0xc000895c + printf("--------------------------------------------------\n"); + for (i = 0; i < 16; i++) { + printf("[R%02d]:[0x%08x]\t", i, state->Reg[i]); + if ((i % 3) == 2) { + printf("\n"); + } + } + printf("[cpr]:[0x%08x]\t[spr0]:[0x%08x]\n", state->Cpsr, state->Spsr[0]); + for (j = 1; j < 7; j++) { + printf("[spr%d]:[0x%08x]\t", j, state->Spsr[j]); + if ((j % 4) == 3) { + printf("\n"); + } + } + printf("\n[PC]:[0x%08x]\t[INST]:[0x%08x]\t[COUNT]:[%d]\n", pc, instr, instr_sum); + printf("--------------------------------------------------\n"); + } +#endif + +#if 0 + fprintf(state->state_log, "PC:0x%x\n", pc); + for (reg_index = 0; reg_index < 16; reg_index ++) { + if (state->Reg[reg_index] != mirror_register_file[reg_index]) { + fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]); + mirror_register_file[reg_index] = state->Reg[reg_index]; + } + } + if (state->Cpsr != mirror_register_file[CPSR_REG]) { + fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr); + mirror_register_file[CPSR_REG] = state->Cpsr; + } + if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) { + fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]); + mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; + } + if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) { + fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]); + mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; + } + if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) { + fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]); + mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13]; + } + if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) { + fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]); + mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14]; + } + if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) { + fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]); + mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13]; + } + if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) { + fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]); + mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14]; + } + if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) { + fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]); + mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13]; + } + if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) { + fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]); + mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14]; + } + if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) { + fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]); + mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8]; + } + if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) { + fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]); + mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9]; + } + if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) { + fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]); + mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10]; + } + if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) { + fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]); + mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11]; + } + if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) { + fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]); + mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12]; + } + if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) { + fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]); + mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13]; + } + if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) { + fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]); + mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14]; + } + if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) { + fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]); + mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK]; + } + if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) { + fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]); + mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK]; + } + if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) { + fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]); + mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK]; + } + if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) { + fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]); + mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK]; + } + if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) { + fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]); + mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK]; + } + +#endif + +#ifdef NEED_UI_LOOP_HOOK + if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + ui_loop_hook (0); + } +#endif /* NEED_UI_LOOP_HOOK */ + + /*added energy_prof statement by ksh in 2004-11-26 */ + //chy 2005-07-28 for standalone + //ARMul_do_energy(state,instr,pc); +//teawater add for record reg value to ./reg.txt 2005.07.10--------------------- + if (state->tea_break_ok && pc == state->tea_break_addr) { + //ARMul_Debug (state, 0, 0); + state->tea_break_ok = 0; + } else { + state->tea_break_ok = 1; + } +//AJ2D-------------------------------------------------------------------------- +//chy 2006-04-14 for ctrl-c debug +#if 0 + if (debugmode) { + if (instr != ARMul_ABORTWORD) { + remote_interrupt_test_time++; + //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!! + if (remote_interrupt_test_time >= 2000) { + remote_interrupt_test_time=0; + if (remote_interrupt()) { + //for test + //printf("SKYEYE: ICE_debug recv Ctrl_C\n"); + state->EndCondition = 0; + state->Emulate = STOP; + } + } + } + } +#endif + + /* jump out every time */ + //state->EndCondition = 0; + //state->Emulate = STOP; +//chy 2006-04-12 for ICE debug +TEST_EMULATE: + if (state->Emulate == ONCE) + state->Emulate = STOP; + //chy: 2003-08-23: should not use CHANGEMODE !!!! + /* If we have changed mode, allow the PC to advance before stopping. */ + // else if (state->Emulate == CHANGEMODE) + // continue; + else if (state->Emulate != RUN) + break; + } + + while (state->NumInstrsToExecute); +exit: + state->decoded = decoded; + state->loaded = loaded; + state->pc = pc; + //chy 2006-04-12, for ICE debug + state->decoded_addr=decoded_addr; + state->loaded_addr=loaded_addr; + + return pc; + } + +//teawater add for arm2x86 2005.02.17------------------------------------------- + /*ywc 2005-04-01*/ +//#include "tb.h" +//#include "arm2x86_self.h" + + static volatile void (*gen_func) (void); +//static volatile ARMul_State *tmp_st; +//static volatile ARMul_State *save_st; + static volatile uint32_t tmp_st; + static volatile uint32_t save_st; + static volatile uint32_t save_T0; + static volatile uint32_t save_T1; + static volatile uint32_t save_T2; + +#ifdef MODE32 +#ifdef DBCT +//teawater change for debug function 2005.07.09--------------------------------- + ARMword + ARMul_Emulate32_dbct (ARMul_State * state) { + static int init = 0; + static FILE *fd; + + /*if (!init) { + fd = fopen("./pc.txt", "w"); + if (!fd) { + exit(-1); + } + init = 1; + } */ + + state->Reg[15] += INSN_SIZE; + do { + /*if (skyeye_config.log.logon>=1) { + if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) { + static int mybegin=0; + static int myinstrnum=0; + + if (mybegin==0) mybegin=1; + if (mybegin==1) { + state->Reg[15] -= INSN_SIZE; + if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr); + if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd); + if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd); + fprintf(skyeye_logfd,"\n"); + if (skyeye_config.log.length>0) { + myinstrnum++; + if (myinstrnum>=skyeye_config.log.length) { + myinstrnum=0; + fflush(skyeye_logfd); + fseek(skyeye_logfd,0L,SEEK_SET); + } + } + state->Reg[15] += INSN_SIZE; + } + } + } */ + state->trap = 0; + gen_func = + (void *) tb_find (state, state->Reg[15] - INSN_SIZE); + if (!gen_func) { + //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n"); + //exit(-1); + //TRAP_INSN_ABORT + //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); + //TEA_OUT(printf("TRAP_INSN_ABORT\n")); +//teawater add for xscale(arm v5) 2005.09.01------------------------------------ + /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE); + state->Reg[15] += INSN_SIZE; + ARMul_Abort(state, ARMul_PrefetchAbortV); + state->Reg[15] += INSN_SIZE; + goto next; */ + state->trap = TRAP_INSN_ABORT; + goto check; +//AJ2D-------------------------------------------------------------------------- + } + + save_st = (uint32_t) st; + save_T0 = T0; + save_T1 = T1; + save_T2 = T2; + tmp_st = (uint32_t) state; + wmb (); + st = (ARMul_State *) tmp_st; + gen_func (); + st = (ARMul_State *) save_st; + T0 = save_T0; + T1 = save_T1; + T2 = save_T2; + + /*if (state->trap != TRAP_OUT) { + state->tea_break_ok = 1; + } + if (state->trap <= TRAP_SET_R15) { + goto next; + } */ + //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); +//teawater add check thumb 2005.07.21------------------------------------------- + /*if (TFLAG) { + state->Reg[15] -= 2; + return(state->Reg[15]); + } */ +//AJ2D-------------------------------------------------------------------------- + +//teawater add for xscale(arm v5) 2005.09.01------------------------------------ +check: +//AJ2D-------------------------------------------------------------------------- + switch (state->trap) { + case TRAP_RESET: { + //TEA_OUT(printf("TRAP_RESET\n")); + ARMul_Abort (state, ARMul_ResetV); + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_UNPREDICTABLE: { + //ARMul_Debug (state, 0, 0); + } + break; + case TRAP_INSN_UNDEF: { + //TEA_OUT(printf("TRAP_INSN_UNDEF\n")); + state->Reg[15] += INSN_SIZE; + ARMul_UndefInstr (state, 0); + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_SWI: { + //TEA_OUT(printf("TRAP_SWI\n")); + state->Reg[15] += INSN_SIZE; + ARMul_Abort (state, ARMul_SWIV); + state->Reg[15] += INSN_SIZE; + } + break; +//teawater add for xscale(arm v5) 2005.09.01------------------------------------ + case TRAP_INSN_ABORT: { + /*XScale_set_fsr_far (state, + ARMul_CP15_R5_MMU_EXCPT, + state->Reg[15] - + INSN_SIZE);*/ + state->Reg[15] += INSN_SIZE; + ARMul_Abort (state, ARMul_PrefetchAbortV); + state->Reg[15] += INSN_SIZE; + } + break; +//AJ2D-------------------------------------------------------------------------- + case TRAP_DATA_ABORT: { + //TEA_OUT(printf("TRAP_DATA_ABORT\n")); + state->Reg[15] += INSN_SIZE; + ARMul_Abort (state, ARMul_DataAbortV); + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_IRQ: { + //TEA_OUT(printf("TRAP_IRQ\n")); + state->Reg[15] += INSN_SIZE; + ARMul_Abort (state, ARMul_IRQV); + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_FIQ: { + //TEA_OUT(printf("TRAP_FIQ\n")); + state->Reg[15] += INSN_SIZE; + ARMul_Abort (state, ARMul_FIQV); + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_SETS_R15: { + //TEA_OUT(printf("TRAP_SETS_R15\n")); + /*if (state->Bank > 0) { + state->Cpsr = state->Spsr[state->Bank]; + ARMul_CPSRAltered (state); + } */ + WriteSR15 (state, state->Reg[15]); + } + break; + case TRAP_SET_CPSR: { + //TEA_OUT(printf("TRAP_SET_CPSR\n")); + //chy 2006-02-15 USERBANK=SYSTEMBANK=0 + //chy 2006-02-16 should use Mode to test + //if (state->Bank > 0) { + if (state->Mode != USER26MODE && state->Mode != USER32MODE) { + //ARMul_CPSRAltered (state); + } + state->Reg[15] += INSN_SIZE; + } + break; + case TRAP_OUT: { + //TEA_OUT(printf("TRAP_OUT\n")); + goto out; + } + break; + case TRAP_BREAKPOINT: { + //TEA_OUT(printf("TRAP_BREAKPOINT\n")); + state->Reg[15] -= INSN_SIZE; + if (!ARMul_OSHandleSWI + (state, SWI_Breakpoint)) { + ARMul_Abort (state, ARMul_SWIV); + } + state->Reg[15] += INSN_SIZE; + } + break; + } + +next: + if (state->Emulate == ONCE) { + state->Emulate = STOP; + break; + } else if (state->Emulate != RUN) { + break; + } + } while (!state->stop_simulator); + +out: + state->Reg[15] -= INSN_SIZE; + return (state->Reg[15]); + } +#endif +//AJ2D-------------------------------------------------------------------------- +#endif +//AJ2D-------------------------------------------------------------------------- + + /* This routine evaluates most Data Processing register RHS's with the S + bit clear. It is intended to be called from the macro DPRegRHS, which + filters the common case of an unshifted register with in line code. */ + + static ARMword + GetDPRegRHS (ARMul_State * state, ARMword instr) { + ARMword shamt, base; + + base = RHSReg; + if (BIT (4)) { + /* Shift amount in a register. */ + UNDEF_Shift; + INCPC; +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + ARMul_Icycles (state, 1, 0L); + shamt = state->Reg[BITS (8, 11)] & 0xff; + switch ((int) BITS (5, 6)) { + case LSL: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return (0); + else + return (base << shamt); + case LSR: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return ((ARMword) ((int) base >> 31L)); + else + return ((ARMword) + (( int) base >> (int) shamt)); + case ROR: + shamt &= 0x1f; + if (shamt == 0) + return (base); + else + return ((base << (32 - shamt)) | + (base >> shamt)); + } + } else { + /* Shift amount is a constant. */ +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + shamt = BITS (7, 11); + switch ((int) BITS (5, 6)) { + case LSL: + return (base << shamt); + case LSR: + if (shamt == 0) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return ((ARMword) (( int) base >> 31L)); + else + return ((ARMword) + (( int) base >> (int) shamt)); + case ROR: + if (shamt == 0) + /* It's an RRX. */ + return ((base >> 1) | (CFLAG << 31)); + else + return ((base << (32 - shamt)) | + (base >> shamt)); + } + } + + return 0; + } + + /* This routine evaluates most Logical Data Processing register RHS's + with the S bit set. It is intended to be called from the macro + DPSRegRHS, which filters the common case of an unshifted register + with in line code. */ + + static ARMword + GetDPSRegRHS (ARMul_State * state, ARMword instr) { + ARMword shamt, base; + + base = RHSReg; + if (BIT (4)) { + /* Shift amount in a register. */ + UNDEF_Shift; + INCPC; +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + ARMul_Icycles (state, 1, 0L); + shamt = state->Reg[BITS (8, 11)] & 0xff; + switch ((int) BITS (5, 6)) { + case LSL: + if (shamt == 0) + return (base); + else if (shamt == 32) { + ASSIGNC (base & 1); + return (0); + } else if (shamt > 32) { + CLEARC; + return (0); + } else { + ASSIGNC ((base >> (32 - shamt)) & 1); + return (base << shamt); + } + case LSR: + if (shamt == 0) + return (base); + else if (shamt == 32) { + ASSIGNC (base >> 31); + return (0); + } else if (shamt > 32) { + CLEARC; + return (0); + } else { + ASSIGNC ((base >> (shamt - 1)) & 1); + return (base >> shamt); + } + case ASR: + if (shamt == 0) + return (base); + else if (shamt >= 32) { + ASSIGNC (base >> 31L); + return ((ARMword) (( int) base >> 31L)); + } else { + ASSIGNC ((ARMword) + (( int) base >> + (int) (shamt - 1)) & 1); + return ((ARMword) + ((int) base >> (int) shamt)); + } + case ROR: + if (shamt == 0) + return (base); + shamt &= 0x1f; + if (shamt == 0) { + ASSIGNC (base >> 31); + return (base); + } else { + ASSIGNC ((base >> (shamt - 1)) & 1); + return ((base << (32 - shamt)) | + (base >> shamt)); + } + } + } else { + /* Shift amount is a constant. */ +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + shamt = BITS (7, 11); + + switch ((int) BITS (5, 6)) { + case LSL: + ASSIGNC ((base >> (32 - shamt)) & 1); + return (base << shamt); + case LSR: + if (shamt == 0) { + ASSIGNC (base >> 31); + return (0); + } else { + ASSIGNC ((base >> (shamt - 1)) & 1); + return (base >> shamt); + } + case ASR: + if (shamt == 0) { + ASSIGNC (base >> 31L); + return ((ARMword) ((int) base >> 31L)); + } else { + ASSIGNC ((ARMword) + ((int) base >> + (int) (shamt - 1)) & 1); + return ((ARMword) + (( int) base >> (int) shamt)); + } + case ROR: + if (shamt == 0) { + /* It's an RRX. */ + shamt = CFLAG; + ASSIGNC (base & 1); + return ((base >> 1) | (shamt << 31)); + } else { + ASSIGNC ((base >> (shamt - 1)) & 1); + return ((base << (32 - shamt)) | + (base >> shamt)); + } + } + } + + return 0; + } + + /* This routine handles writes to register 15 when the S bit is not set. */ + + static void + WriteR15 (ARMul_State * state, ARMword src) { + /* The ARM documentation states that the two least significant bits + are discarded when setting PC, except in the cases handled by + WriteR15Branch() below. It's probably an oversight: in THUMB + mode, the second least significant bit should probably not be + discarded. */ +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; + +#ifdef MODE32 + state->Reg[15] = src & PCBITS; +#else + state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE; + ARMul_R15Altered (state); +#endif + + FLUSHPIPE; + } + + /* This routine handles writes to register 15 when the S bit is set. */ + + static void + WriteSR15 (ARMul_State * state, ARMword src) { +#ifdef MODE32 + if (state->Bank > 0) { + state->Cpsr = state->Spsr[state->Bank]; + ARMul_CPSRAltered (state); + } +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; + state->Reg[15] = src & PCBITS; +#else +#ifdef MODET + if (TFLAG) + /* ARMul_R15Altered would have to support it. */ + abort (); + else +#endif + src &= 0xfffffffc; + + if (state->Bank == USERBANK) + state->Reg[15] = + (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; + else + state->Reg[15] = src; + + ARMul_R15Altered (state); +#endif + FLUSHPIPE; + } + + /* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM + will switch to Thumb mode if the least significant bit is set. */ + + static void + WriteR15Branch (ARMul_State * state, ARMword src) { +#ifdef MODET + if (src & 1) { + /* Thumb bit. */ + SETT; + state->Reg[15] = src & 0xfffffffe; + } else { + CLEART; + state->Reg[15] = src & 0xfffffffc; + } + state->Cpsr = ARMul_GetCPSR (state); + FLUSHPIPE; +#else + WriteR15 (state, src); +#endif + } + + /* This routine evaluates most Load and Store register RHS's. It is + intended to be called from the macro LSRegRHS, which filters the + common case of an unshifted register with in line code. */ + + static ARMword + GetLSRegRHS (ARMul_State * state, ARMword instr) { + ARMword shamt, base; + + base = RHSReg; +#ifndef MODE32 + if (base == 15) + /* Now forbidden, but ... */ + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + + shamt = BITS (7, 11); + switch ((int) BITS (5, 6)) { + case LSL: + return (base << shamt); + case LSR: + if (shamt == 0) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return ((ARMword) (( int) base >> 31L)); + else + return ((ARMword) (( int) base >> (int) shamt)); + case ROR: + if (shamt == 0) + /* It's an RRX. */ + return ((base >> 1) | (CFLAG << 31)); + else + return ((base << (32 - shamt)) | (base >> shamt)); + default: + break; + } + return 0; + } + + /* This routine evaluates the ARM7T halfword and signed transfer RHS's. */ + + static ARMword + GetLS7RHS (ARMul_State * state, ARMword instr) { + if (BIT (22) == 0) { + /* Register. */ +#ifndef MODE32 + if (RHSReg == 15) + /* Now forbidden, but ... */ + return ECC | ER15INT | R15PC | EMODE; +#endif + return state->Reg[RHSReg]; + } + + /* Immediate. */ + return BITS (0, 3) | (BITS (8, 11) << 4); + } + + /* This function does the work of loading a word for a LDR instruction. */ +#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ + fprintf(skyeye_logfd, \ + "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \ + description, state->NumInstrs, state->pc, instr, \ + address, dest); \ + } + +#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ + fprintf(skyeye_logfd, \ + "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \ + description, state->NumInstrs, state->pc, instr, \ + address, DEST); \ + } + + static unsigned + LoadWord (ARMul_State * state, ARMword instr, ARMword address) { + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + + dest = ARMul_LoadWordN (state, address); + + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + if (address & 3) + dest = ARMul_Align (state, address, dest); + WRITEDESTB (dest); + ARMul_Icycles (state, 1, 0L); + + //MEM_LOAD_LOG("WORD"); + + return (DESTReg != LHSReg); + } + +#ifdef MODET + /* This function does the work of loading a halfword. */ + + static unsigned + LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address, + int signextend) { + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + dest = ARMul_LoadHalfWord (state, address); + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + UNDEF_LSRBPC; + if (signextend) + if (dest & 1 << (16 - 1)) + dest = (dest & ((1 << 16) - 1)) - (1 << 16); + + WRITEDEST (dest); + ARMul_Icycles (state, 1, 0L); + + //MEM_LOAD_LOG("HALFWORD"); + + return (DESTReg != LHSReg); + } + +#endif /* MODET */ + + /* This function does the work of loading a byte for a LDRB instruction. */ + + static unsigned + LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) { + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + dest = ARMul_LoadByte (state, address); + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + UNDEF_LSRBPC; + if (signextend) + if (dest & 1 << (8 - 1)) + dest = (dest & ((1 << 8) - 1)) - (1 << 8); + + WRITEDEST (dest); + ARMul_Icycles (state, 1, 0L); + + //MEM_LOAD_LOG("BYTE"); + + return (DESTReg != LHSReg); + } + + /* This function does the work of loading two words for a LDRD instruction. */ + + static void + Handle_Load_Double (ARMul_State * state, ARMword instr) { + ARMword dest_reg; + ARMword addr_reg; + ARMword write_back = BIT (21); + ARMword immediate = BIT (22); + ARMword add_to_base = BIT (23); + ARMword pre_indexed = BIT (24); + ARMword offset; + ARMword addr; + ARMword sum; + ARMword base; + ARMword value1; + ARMword value2; + + BUSUSEDINCPCS; + + /* If the writeback bit is set, the pre-index bit must be clear. */ + if (write_back && !pre_indexed) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the base address register. */ + addr_reg = LHSReg; + + /* Extract the destination register and check it. */ + dest_reg = DESTReg; + + /* Destination register must be even. */ + if ((dest_reg & 1) + /* Destination register cannot be LR. */ + || (dest_reg == 14)) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Compute the base address. */ + base = state->Reg[addr_reg]; + + /* Compute the offset. */ + offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> + Reg[RHSReg]; + + /* Compute the sum of the two. */ + if (add_to_base) + sum = base + offset; + else + sum = base - offset; + + /* If this is a pre-indexed mode use the sum. */ + if (pre_indexed) + addr = sum; + else + addr = base; + + /* The address must be aligned on a 8 byte boundary. */ + /*if (addr & 0x7) { + #ifdef ABORTS + ARMul_DATAABORT (addr); + #else + ARMul_UndefInstr (state, instr); + #endif + return; + }*/ + /* Lets just forcibly align it for now */ + //addr = (addr + 7) & ~7; + + /* For pre indexed or post indexed addressing modes, + check that the destination registers do not overlap + the address registers. */ + if ((!pre_indexed || write_back) + && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Load the words. */ + value1 = ARMul_LoadWordN (state, addr); + value2 = ARMul_LoadWordN (state, addr + 4); + + /* Check for data aborts. */ + if (state->Aborted) { + TAKEABORT; + return; + } + + ARMul_Icycles (state, 2, 0L); + + /* Store the values. */ + state->Reg[dest_reg] = value1; + state->Reg[dest_reg + 1] = value2; + + /* Do the post addressing and writeback. */ + if (!pre_indexed) + addr = sum; + + if (!pre_indexed || write_back) + state->Reg[addr_reg] = addr; + } + + /* This function does the work of storing two words for a STRD instruction. */ + + static void + Handle_Store_Double (ARMul_State * state, ARMword instr) { + ARMword src_reg; + ARMword addr_reg; + ARMword write_back = BIT (21); + ARMword immediate = BIT (22); + ARMword add_to_base = BIT (23); + ARMword pre_indexed = BIT (24); + ARMword offset; + ARMword addr; + ARMword sum; + ARMword base; + + BUSUSEDINCPCS; + + /* If the writeback bit is set, the pre-index bit must be clear. */ + if (write_back && !pre_indexed) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the base address register. */ + addr_reg = LHSReg; + + /* Base register cannot be PC. */ + if (addr_reg == 15) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the source register. */ + src_reg = DESTReg; + + /* Source register must be even. */ + if (src_reg & 1) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Compute the base address. */ + base = state->Reg[addr_reg]; + + /* Compute the offset. */ + offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> + Reg[RHSReg]; + + /* Compute the sum of the two. */ + if (add_to_base) + sum = base + offset; + else + sum = base - offset; + + /* If this is a pre-indexed mode use the sum. */ + if (pre_indexed) + addr = sum; + else + addr = base; + + /* The address must be aligned on a 8 byte boundary. */ + /*if (addr & 0x7) { + #ifdef ABORTS + ARMul_DATAABORT (addr); + #else + ARMul_UndefInstr (state, instr); + #endif + return; + }*/ + /* Lets just forcibly align it for now */ + //addr = (addr + 7) & ~7; + + /* For pre indexed or post indexed addressing modes, + check that the destination registers do not overlap + the address registers. */ + if ((!pre_indexed || write_back) + && (addr_reg == src_reg || addr_reg == src_reg + 1)) { + ARMul_UndefInstr (state, instr); + return; + } + + /* Load the words. */ + ARMul_StoreWordN (state, addr, state->Reg[src_reg]); + ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]); + + if (state->Aborted) { + TAKEABORT; + return; + } + + /* Do the post addressing and writeback. */ + if (!pre_indexed) + addr = sum; + + if (!pre_indexed || write_back) + state->Reg[addr_reg] = addr; + } + + /* This function does the work of storing a word from a STR instruction. */ + + static unsigned + StoreWord (ARMul_State * state, ARMword instr, ARMword address) { + //MEM_STORE_LOG("WORD"); + + BUSUSEDINCPCN; +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif +#ifdef MODE32 + ARMul_StoreWordN (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) { + INTERNALABORT (address); + (void) ARMul_LoadWordN (state, address); + } else + ARMul_StoreWordN (state, address, DEST); +#endif + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + + return TRUE; + } + +#ifdef MODET + /* This function does the work of storing a byte for a STRH instruction. */ + + static unsigned + StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) { + //MEM_STORE_LOG("HALFWORD"); + + BUSUSEDINCPCN; + +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif + +#ifdef MODE32 + ARMul_StoreHalfWord (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) { + INTERNALABORT (address); + (void) ARMul_LoadHalfWord (state, address); + } else + ARMul_StoreHalfWord (state, address, DEST); +#endif + + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + return TRUE; + } + +#endif /* MODET */ + + /* This function does the work of storing a byte for a STRB instruction. */ + + static unsigned + StoreByte (ARMul_State * state, ARMword instr, ARMword address) { + //MEM_STORE_LOG("BYTE"); + + BUSUSEDINCPCN; +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif +#ifdef MODE32 + ARMul_StoreByte (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) { + INTERNALABORT (address); + (void) ARMul_LoadByte (state, address); + } else + ARMul_StoreByte (state, address, DEST); +#endif + if (state->Aborted) { + TAKEABORT; + return state->lateabtSig; + } + //UNDEF_LSRBPC; + return TRUE; + } + + /* This function does the work of loading the registers listed in an LDM + instruction, when the S bit is clear. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + + static void + LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) { + ARMword dest, temp; + + //UNDEF_LSMNoRegs; + //UNDEF_LSMPCBase; + //UNDEF_LSMBaseInListWb; + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + /*chy 2004-05-23 may write twice + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + */ + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp++); + + dest = ARMul_LoadWordN (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp++] = dest; + else if (!state->Aborted) { + //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + /*chy 2004-05-23 chy goto end*/ + if (state->Aborted) + goto L_ldm_makeabort; + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) { + /* Load this register. */ + address += 4; + dest = ARMul_LoadWordS (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp] = dest; + else if (!state->Aborted) { + /*XScale_set_fsr_far (state, + ARMul_CP15_R5_ST_ALIGN, + address);*/ + state->Aborted = ARMul_DataAbortV; + } + /*chy 2004-05-23 chy goto end */ + if (state->Aborted) + goto L_ldm_makeabort; + } + + if (BIT (15) && !state->Aborted) + /* PC is in the reg list. */ + WriteR15Branch (state, PC); + + /* To write back the final register. */ + /* ARMul_Icycles (state, 1, 0L);*/ + /*chy 2004-05-23, see below + if (state->Aborted) + { + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + TAKEABORT; + } + */ + /*chy 2004-05-23 should compare the Abort Models*/ +L_ldm_makeabort: + /* To write back the final register. */ + ARMul_Icycles (state, 1, 0L); + + /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */ + /* + if (state->Aborted) + { + if (BIT (21) && LHSReg != 15) + if (!(state->abortSig && state->Aborted && state->lateabtSig == LOW)) + LSBase = WBBase; + TAKEABORT; + }else if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + */ + if (state->Aborted) { + if (BIT (21) && LHSReg != 15) { + if (!(state->abortSig)) { + } + } + TAKEABORT; + } else if (BIT (21) && LHSReg != 15) { + LSBase = WBBase; + } + /* chy 2005-11-24, over */ + } + + /* This function does the work of loading the registers listed in an LDM + instruction, when the S bit is set. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + + static void + LoadSMult (ARMul_State * state, + ARMword instr, ARMword address, ARMword WBBase) { + ARMword dest, temp; + + //UNDEF_LSMNoRegs; + //UNDEF_LSMPCBase; + //UNDEF_LSMBaseInListWb; + + BUSUSEDINCPCS; + +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + /* chy 2004-05-23, may write twice + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + */ + if (!BIT (15) && state->Bank != USERBANK) { + /* Temporary reg bank switch. */ + (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); + UNDEF_LSMUserBankWb; + } + + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp++); + + dest = ARMul_LoadWordN (state, address); + + if (!state->abortSig) + state->Reg[temp++] = dest; + else if (!state->Aborted) { + //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + + /*chy 2004-05-23 chy goto end*/ + if (state->Aborted) + goto L_ldm_s_makeabort; + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) { + /* Load this register. */ + address += 4; + dest = ARMul_LoadWordS (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp] = dest; + else if (!state->Aborted) { + /*XScale_set_fsr_far (state, + ARMul_CP15_R5_ST_ALIGN, + address);*/ + state->Aborted = ARMul_DataAbortV; + } + /*chy 2004-05-23 chy goto end */ + if (state->Aborted) + goto L_ldm_s_makeabort; + } + + /*chy 2004-05-23 label of ldm_s_makeabort*/ +L_ldm_s_makeabort: + /*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/ + /*chy 2004-05-23 should compare the Abort Models*/ + if (state->Aborted) { + if (BIT (21) && LHSReg != 15) + if (! + (state->abortSig && state->Aborted + && state->lateabtSig == LOW)) + LSBase = WBBase; + TAKEABORT; + } else if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + if (BIT (15) && !state->Aborted) { + /* PC is in the reg list. */ +#ifdef MODE32 + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (state->Mode != USER26MODE && state->Mode != USER32MODE ) { + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); + } + + WriteR15 (state, PC); +#else + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (state->Mode == USER26MODE || state->Mode == USER32MODE ) { + /* Protect bits in user mode. */ + ASSIGNN ((state->Reg[15] & NBIT) != 0); + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); + ASSIGNC ((state->Reg[15] & CBIT) != 0); + ASSIGNV ((state->Reg[15] & VBIT) != 0); + } else + ARMul_R15Altered (state); + + FLUSHPIPE; +#endif + } + + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (!BIT (15) && state->Mode != USER26MODE + && state->Mode != USER32MODE ) + /* Restore the correct bank. */ + (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); + + /* To write back the final register. */ + ARMul_Icycles (state, 1, 0L); + /* chy 2004-05-23, see below + if (state->Aborted) + { + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + TAKEABORT; + } + */ + } + + /* This function does the work of storing the registers listed in an STM + instruction, when the S bit is clear. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + + static void + StoreMult (ARMul_State * state, + ARMword instr, ARMword address, ARMword WBBase) { + ARMword temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + + if (!TFLAG) + /* N-cycle, increment the PC and update the NextInstr state. */ + BUSUSEDINCPCN; + +#ifndef MODE32 + if (VECTORACCESS (address) || ADDREXCEPT (address)) + INTERNALABORT (address); + + if (BIT (15)) + PATCHR15; +#endif + + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp++); + +#ifdef MODE32 + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#else + if (state->Aborted) { + (void) ARMul_LoadWordN (state, address); + + /* Fake the Stores as Loads. */ + for (; temp < 16; temp++) + if (BIT (temp)) { + /* Save this register. */ + address += 4; + (void) ARMul_LoadWordS (state, address); + } + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + TAKEABORT; + return; + } else + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#endif + + if (state->abortSig && !state->Aborted) { + //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + +//chy 2004-05-23, needn't store other when aborted + if (state->Aborted) + goto L_stm_takeabort; + + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) { + /* Save this register. */ + address += 4; + + ARMul_StoreWordS (state, address, state->Reg[temp]); + + if (state->abortSig && !state->Aborted) { + /*XScale_set_fsr_far (state, + ARMul_CP15_R5_ST_ALIGN, + address);*/ + state->Aborted = ARMul_DataAbortV; + } + //chy 2004-05-23, needn't store other when aborted + if (state->Aborted) + goto L_stm_takeabort; + } + +//chy 2004-05-23,should compare the Abort Models +L_stm_takeabort: + if (BIT (21) && LHSReg != 15) { + if (! + (state->abortSig && state->Aborted + && state->lateabtSig == LOW)) + LSBase = WBBase; + } + if (state->Aborted) + TAKEABORT; + } + + /* This function does the work of storing the registers listed in an STM + instruction when the S bit is set. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + + static void + StoreSMult (ARMul_State * state, + ARMword instr, ARMword address, ARMword WBBase) { + ARMword temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + + BUSUSEDINCPCN; + +#ifndef MODE32 + if (VECTORACCESS (address) || ADDREXCEPT (address)) + INTERNALABORT (address); + + if (BIT (15)) + PATCHR15; +#endif + + if (state->Bank != USERBANK) { + /* Force User Bank. */ + (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); + UNDEF_LSMUserBankWb; + } + + for (temp = 0; !BIT (temp); temp++); /* N cycle first. */ + +#ifdef MODE32 + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#else + if (state->Aborted) { + (void) ARMul_LoadWordN (state, address); + + for (; temp < 16; temp++) + /* Fake the Stores as Loads. */ + if (BIT (temp)) { + /* Save this register. */ + address += 4; + + (void) ARMul_LoadWordS (state, address); + } + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + TAKEABORT; + return; + } else + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#endif + + if (state->abortSig && !state->Aborted) { + //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + +//chy 2004-05-23, needn't store other when aborted + if (state->Aborted) + goto L_stm_s_takeabort; + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) { + /* Save this register. */ + address += 4; + + ARMul_StoreWordS (state, address, state->Reg[temp]); + + if (state->abortSig && !state->Aborted) { + /*XScale_set_fsr_far (state, + ARMul_CP15_R5_ST_ALIGN, + address);*/ + state->Aborted = ARMul_DataAbortV; + } + //chy 2004-05-23, needn't store other when aborted + if (state->Aborted) + goto L_stm_s_takeabort; + } + + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (state->Mode != USER26MODE && state->Mode != USER32MODE ) + /* Restore the correct bank. */ + (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); + +//chy 2004-05-23,should compare the Abort Models +L_stm_s_takeabort: + if (BIT (21) && LHSReg != 15) { + if (! + (state->abortSig && state->Aborted + && state->lateabtSig == LOW)) + LSBase = WBBase; + } + + if (state->Aborted) + TAKEABORT; + } + + /* This function does the work of adding two 32bit values + together, and calculating if a carry has occurred. */ + + static ARMword + Add32 (ARMword a1, ARMword a2, int *carry) { + ARMword result = (a1 + a2); + unsigned int uresult = (unsigned int) result; + unsigned int ua1 = (unsigned int) a1; + + /* If (result == RdLo) and (state->Reg[nRdLo] == 0), + or (result > RdLo) then we have no carry. */ + if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)) + *carry = 1; + else + *carry = 0; + + return result; + } + + /* This function does the work of multiplying + two 32bit values to give a 64bit result. */ + + static unsigned + Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) { + /* Operand register numbers. */ + int nRdHi, nRdLo, nRs, nRm; + ARMword RdHi = 0, RdLo = 0, Rm; + /* Cycle count. */ + int scount; + + nRdHi = BITS (16, 19); + nRdLo = BITS (12, 15); + nRs = BITS (8, 11); + nRm = BITS (0, 3); + + /* Needed to calculate the cycle count. */ + Rm = state->Reg[nRm]; + + /* Check for illegal operand combinations first. */ + if (nRdHi != 15 + && nRdLo != 15 + && nRs != 15 + //&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) { + && nRm != 15 && nRdHi != nRdLo ) { + /* Intermediate results. */ + ARMword lo, mid1, mid2, hi; + int carry; + ARMword Rs = state->Reg[nRs]; + int sign = 0; + + if (msigned) { + /* Compute sign of result and adjust operands if necessary. */ + sign = (Rm ^ Rs) & 0x80000000; + + if (((signed int) Rm) < 0) + Rm = -Rm; + + if (((signed int) Rs) < 0) + Rs = -Rs; + } + + /* We can split the 32x32 into four 16x16 operations. This + ensures that we do not lose precision on 32bit only hosts. */ + lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF)); + mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); + mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF)); + hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); + + /* We now need to add all of these results together, taking + care to propogate the carries from the additions. */ + RdLo = Add32 (lo, (mid1 << 16), &carry); + RdHi = carry; + RdLo = Add32 (RdLo, (mid2 << 16), &carry); + RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + + ((mid2 >> 16) & 0xFFFF) + hi); + + if (sign) { + /* Negate result if necessary. */ + RdLo = ~RdLo; + RdHi = ~RdHi; + if (RdLo == 0xFFFFFFFF) { + RdLo = 0; + RdHi += 1; + } else + RdLo += 1; + } + + state->Reg[nRdLo] = RdLo; + state->Reg[nRdHi] = RdHi; + } else { + fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS, instr=0x%x\n", instr); + } + if (scc) + /* Ensure that both RdHi and RdLo are used to compute Z, + but don't let RdLo's sign bit make it to N. */ + ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); + + /* The cycle count depends on whether the instruction is a signed or + unsigned multiply, and what bits are clear in the multiplier. */ + if (msigned && (Rm & ((unsigned) 1 << 31))) + /* Invert the bits to make the check against zero. */ + Rm = ~Rm; + + if ((Rm & 0xFFFFFF00) == 0) + scount = 1; + else if ((Rm & 0xFFFF0000) == 0) + scount = 2; + else if ((Rm & 0xFF000000) == 0) + scount = 3; + else + scount = 4; + + return 2 + scount; + } + + /* This function does the work of multiplying two 32bit + values and adding a 64bit value to give a 64bit result. */ + + static unsigned + MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc) { + unsigned scount; + ARMword RdLo, RdHi; + int nRdHi, nRdLo; + int carry = 0; + + nRdHi = BITS (16, 19); + nRdLo = BITS (12, 15); + + RdHi = state->Reg[nRdHi]; + RdLo = state->Reg[nRdLo]; + + scount = Multiply64 (state, instr, msigned, LDEFAULT); + + RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry); + RdHi = (RdHi + state->Reg[nRdHi]) + carry; + + state->Reg[nRdLo] = RdLo; + state->Reg[nRdHi] = RdHi; + + if (scc) + /* Ensure that both RdHi and RdLo are used to compute Z, + but don't let RdLo's sign bit make it to N. */ + ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); + + /* Extra cycle for addition. */ + return scount + 1; + } + + /* Attempt to emulate an ARMv6 instruction. + Returns non-zero upon success. */ + + static int handle_v6_insn(ARMul_State* state, ARMword instr) { + switch (BITS(20, 27)) { + case 0x03: + printf ("Unhandled v6 insn: ldr\n"); + break; + case 0x04: // UMAAL + { + const u8 rm_idx = BITS(8, 11); + const u8 rn_idx = BITS(0, 3); + const u8 rd_lo_idx = BITS(12, 15); + const u8 rd_hi_idx = BITS(16, 19); + + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + const u32 rd_lo_val = state->Reg[rd_lo_idx]; + const u32 rd_hi_val = state->Reg[rd_hi_idx]; + + const u64 result = (rn_val * rm_val) + rd_lo_val + rd_hi_val; + + state->Reg[rd_lo_idx] = (result & 0xFFFFFFFF); + state->Reg[rd_hi_idx] = ((result >> 32) & 0xFFFFFFFF); + return 1; + } + break; + case 0x06: + printf ("Unhandled v6 insn: mls/str\n"); + break; + case 0x16: + printf ("Unhandled v6 insn: smi\n"); + break; + case 0x18: + if (BITS(4, 7) == 0x9) { + /* strex */ + u32 l = LHSReg; + u32 r = RHSReg; + u32 lhs = LHS; + + bool enter = false; + + if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr))enter = true; + //StoreWord(state, lhs, RHS) + if (state->Aborted) { + TAKEABORT; + } + + if (enter) { + ARMul_StoreWordS(state, lhs, RHS); + state->Reg[DESTReg] = 0; + } + else { + state->Reg[DESTReg] = 1; + } + + return 1; + } + printf ("Unhandled v6 insn: strex\n"); + break; + case 0x19: + /* ldrex */ + if (BITS(4, 7) == 0x9) { + u32 lhs = LHS; + + state->currentexaddr = lhs; + state->currentexval = ARMul_ReadWord(state, lhs); + + LoadWord(state, instr, lhs); + return 1; + } + printf ("Unhandled v6 insn: ldrex\n"); + break; + case 0x1a: + printf ("Unhandled v6 insn: strexd\n"); + break; + case 0x1b: + printf ("Unhandled v6 insn: ldrexd\n"); + break; + case 0x1c: + if (BITS(4, 7) == 0x9) { + /* strexb */ + u32 lhs = LHS; + + bool enter = false; + + if (state->currentexval == (u32)ARMul_ReadByte(state, state->currentexaddr))enter = true; + + BUSUSEDINCPCN; + if (state->Aborted) { + TAKEABORT; + } + + if (enter) { + ARMul_StoreByte(state, lhs, RHS); + state->Reg[DESTReg] = 0; + } + else { + state->Reg[DESTReg] = 1; + } + + //printf("In %s, strexb not implemented\n", __FUNCTION__); + UNDEF_LSRBPC; + /* WRITESDEST (dest); */ + return 1; + } + printf ("Unhandled v6 insn: strexb\n"); + break; + case 0x1d: + if ((BITS(4, 7)) == 0x9) { + /* ldrexb */ + u32 lhs = LHS; + LoadByte(state, instr, lhs, LUNSIGNED); + + state->currentexaddr = lhs; + state->currentexval = (u32)ARMul_ReadByte(state, lhs); + + //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); + //printf("ldrexb\n"); + //printf("instr is %x rm is %d\n", instr, BITS(16, 19)); + //exit(-1); + + //printf("In %s, ldrexb not implemented\n", __FUNCTION__); + return 1; + } + printf ("Unhandled v6 insn: ldrexb\n"); + break; + case 0x1e: + printf ("Unhandled v6 insn: strexh\n"); + break; + case 0x1f: + printf ("Unhandled v6 insn: ldrexh\n"); + break; + case 0x30: + printf ("Unhandled v6 insn: movw\n"); + break; + case 0x32: + printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n"); + break; + case 0x34: + printf ("Unhandled v6 insn: movt\n"); + break; + case 0x3f: + printf ("Unhandled v6 insn: rbit\n"); + break; + case 0x61: // SADD16, SASX, SSAX, and SSUB16 + if ((instr & 0xFF0) == 0xf10 || (instr & 0xFF0) == 0xf30 || + (instr & 0xFF0) == 0xf50 || (instr & 0xFF0) == 0xf70) + { + const u8 rd_idx = BITS(12, 15); + const u8 rm_idx = BITS(0, 3); + const u8 rn_idx = BITS(16, 19); + const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF); + const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF); + const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF); + const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF); + + s32 lo_result; + s32 hi_result; + + // SADD16 + if ((instr & 0xFF0) == 0xf10) { + lo_result = (rn_lo + rm_lo); + hi_result = (rn_hi + rm_hi); + } + // SASX + else if ((instr & 0xFF0) == 0xf30) { + lo_result = (rn_lo - rm_hi); + hi_result = (rn_hi + rm_lo); + } + // SSAX + else if ((instr & 0xFF0) == 0xf50) { + lo_result = (rn_lo + rm_hi); + hi_result = (rn_hi - rm_lo); + } + // SSUB16 + else { + lo_result = (rn_lo - rm_lo); + hi_result = (rn_hi - rm_hi); + } + + state->Reg[rd_idx] = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + + if (lo_result >= 0) { + state->GEFlag |= (1 << 16); + state->GEFlag |= (1 << 17); + } else { + state->GEFlag &= ~(1 << 16); + state->GEFlag &= ~(1 << 17); + } + + if (hi_result >= 0) { + state->GEFlag |= (1 << 18); + state->GEFlag |= (1 << 19); + } else { + state->GEFlag &= ~(1 << 18); + state->GEFlag &= ~(1 << 19); + } + + return 1; + } + // SADD8/SSUB8 + else if ((instr & 0xFF0) == 0xf90 || (instr & 0xFF0) == 0xff0) + { + const u8 rd_idx = BITS(12, 15); + const u8 rm_idx = BITS(0, 3); + const u8 rn_idx = BITS(16, 19); + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + s32 lo_val1, lo_val2; + s32 hi_val1, hi_val2; + + // SADD8 + if ((instr & 0xFF0) == 0xf90) { + lo_val1 = (s32)(s8)(rn_val & 0xFF) + (s32)(s8)(rm_val & 0xFF); + lo_val2 = (s32)(s8)((rn_val >> 8) & 0xFF) + (s32)(s8)((rm_val >> 8) & 0xFF); + hi_val1 = (s32)(s8)((rn_val >> 16) & 0xFF) + (s32)(s8)((rm_val >> 16) & 0xFF); + hi_val2 = (s32)(s8)((rn_val >> 24) & 0xFF) + (s32)(s8)((rm_val >> 24) & 0xFF); + } + // SSUB8 + else { + lo_val1 = (s32)(s8)(rn_val & 0xFF) - (s32)(s8)(rm_val & 0xFF); + lo_val2 = (s32)(s8)((rn_val >> 8) & 0xFF) - (s32)(s8)((rm_val >> 8) & 0xFF); + hi_val1 = (s32)(s8)((rn_val >> 16) & 0xFF) - (s32)(s8)((rm_val >> 16) & 0xFF); + hi_val2 = (s32)(s8)((rn_val >> 24) & 0xFF) - (s32)(s8)((rm_val >> 24) & 0xFF); + } + + if (lo_val1 >= 0) + state->GEFlag |= (1 << 16); + else + state->GEFlag &= ~(1 << 16); + + if (lo_val2 >= 0) + state->GEFlag |= (1 << 17); + else + state->GEFlag &= ~(1 << 17); + + if (hi_val1 >= 0) + state->GEFlag |= (1 << 18); + else + state->GEFlag &= ~(1 << 18); + + if (hi_val2 >= 0) + state->GEFlag |= (1 << 19); + else + state->GEFlag &= ~(1 << 19); + + state->Reg[rd_idx] = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24)); + return 1; + } + else { + printf("Unhandled v6 insn: %08x", instr); + } + break; + case 0x62: // QADD16, QASX, QSAX, QSUB16, QADD8, and QSUB8 + { + const u8 op2 = BITS(5, 7); + + const u8 rd_idx = BITS(12, 15); + const u8 rn_idx = BITS(16, 19); + const u8 rm_idx = BITS(0, 3); + const u16 rm_lo = (state->Reg[rm_idx] & 0xFFFF); + const u16 rm_hi = ((state->Reg[rm_idx] >> 0x10) & 0xFFFF); + const u16 rn_lo = (state->Reg[rn_idx] & 0xFFFF); + const u16 rn_hi = ((state->Reg[rn_idx] >> 0x10) & 0xFFFF); + + u16 lo_result = 0; + u16 hi_result = 0; + + // QADD16 + if (op2 == 0x00) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi); + } + // QASX + else if (op2 == 0x01) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo); + } + // QSAX + else if (op2 == 0x02) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo); + } + // QSUB16 + else if (op2 == 0x03) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi); + } + // QADD8 + else if (op2 == 0x04) { + lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8; + } + // QSUB8 + else if (op2 == 0x07) { + lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8; + } + + state->Reg[rd_idx] = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + return 1; + } + break; + case 0x63: + printf ("Unhandled v6 insn: shadd/shsub\n"); + break; + case 0x65: + { + u32 rd = (instr >> 12) & 0xF; + u32 rn = (instr >> 16) & 0xF; + u32 rm = (instr >> 0) & 0xF; + u32 from = state->Reg[rn]; + u32 to = state->Reg[rm]; + + if ((instr & 0xFF0) == 0xF10 || (instr & 0xFF0) == 0xF70) { // UADD16/USUB16 + u32 h1, h2; + state->Cpsr &= 0xfff0ffff; + if ((instr & 0x0F0) == 0x070) { // USUB16 + h1 = ((u16)from - (u16)to); + h2 = ((u16)(from >> 16) - (u16)(to >> 16)); + + if (!(h1 & 0xffff0000)) + state->GEFlag |= (3 << 16); + else + state->GEFlag &= ~(3 << 16); + + if (!(h2 & 0xffff0000)) + state->GEFlag |= (3 << 18); + else + state->GEFlag &= ~(3 << 18); + } + else { // UADD16 + h1 = ((u16)from + (u16)to); + h2 = ((u16)(from >> 16) + (u16)(to >> 16)); + + if (h1 & 0xffff0000) + state->GEFlag |= (3 << 16); + else + state->GEFlag &= ~(3 << 16); + + if (h2 & 0xffff0000) + state->GEFlag |= (3 << 18); + else + state->GEFlag &= ~(3 << 18); + } + + state->Reg[rd] = (u32)((h1 & 0xffff) | ((h2 & 0xffff) << 16)); + return 1; + } + else + if ((instr & 0xFF0) == 0xF90 || (instr & 0xFF0) == 0xFF0) { // UADD8/USUB8 + u32 b1, b2, b3, b4; + state->Cpsr &= 0xfff0ffff; + if ((instr & 0x0F0) == 0x0F0) { // USUB8 + b1 = ((u8)from - (u8)to); + b2 = ((u8)(from >> 8) - (u8)(to >> 8)); + b3 = ((u8)(from >> 16) - (u8)(to >> 16)); + b4 = ((u8)(from >> 24) - (u8)(to >> 24)); + + if (!(b1 & 0xffffff00)) + state->GEFlag |= (1 << 16); + else + state->GEFlag &= ~(1 << 16); + + if (!(b2 & 0xffffff00)) + state->GEFlag |= (1 << 17); + else + state->GEFlag &= ~(1 << 17); + + if (!(b3 & 0xffffff00)) + state->GEFlag |= (1 << 18); + else + state->GEFlag &= ~(1 << 18); + + if (!(b4 & 0xffffff00)) + state->GEFlag |= (1 << 19); + else + state->GEFlag &= ~(1 << 19); + } + else { // UADD8 + b1 = ((u8)from + (u8)to); + b2 = ((u8)(from >> 8) + (u8)(to >> 8)); + b3 = ((u8)(from >> 16) + (u8)(to >> 16)); + b4 = ((u8)(from >> 24) + (u8)(to >> 24)); + + if (b1 & 0xffffff00) + state->GEFlag |= (1 << 16); + else + state->GEFlag &= ~(1 << 16); + + if (b2 & 0xffffff00) + state->GEFlag |= (1 << 17); + else + state->GEFlag &= ~(1 << 17); + + if (b3 & 0xffffff00) + state->GEFlag |= (1 << 18); + else + state->GEFlag &= ~(1 << 18); + + if (b4 & 0xffffff00) + state->GEFlag |= (1 << 19); + else + state->GEFlag &= ~(1 << 19); + } + + state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24); + return 1; + } + } + printf("Unhandled v6 insn: uasx/usax\n"); + break; + case 0x66: // UQADD16, UQASX, UQSAX, UQSUB16, UQADD8, and UQSUB8 + { + const u8 rd_idx = BITS(12, 15); + const u8 rm_idx = BITS(0, 3); + const u8 rn_idx = BITS(16, 19); + const u8 op2 = BITS(5, 7); + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + u16 lo_val = 0; + u16 hi_val = 0; + + // UQADD16 + if (op2 == 0x00) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQASX + else if (op2 == 0x01) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSAX + else if (op2 == 0x02) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSUB16 + else if (op2 == 0x03) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQADD8 + else if (op2 == 0x04) { + lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8; + } + // UQSUB8 + else { + lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) | + ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8; + } + + state->Reg[rd_idx] = ((lo_val & 0xFFFF) | hi_val << 16); + return 1; + } + break; + case 0x67: // UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, and UHSUB8. + { + const u8 op2 = BITS(5, 7); + + const u8 rm_idx = BITS(0, 3); + const u8 rn_idx = BITS(16, 19); + const u8 rd_idx = BITS(12, 15); + + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) + { + u32 lo_val = 0; + u32 hi_val = 0; + + // UHADD16 + if (op2 == 0x00) { + lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + } + // UHASX + else if (op2 == 0x01) { + lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); + } + // UHSAX + else if (op2 == 0x02) { + lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); + } + // UHSUB16 + else if (op2 == 0x03) { + lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + } + + lo_val >>= 1; + hi_val >>= 1; + + state->Reg[rd_idx] = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16); + return 1; + } + else if (op2 == 0x04 || op2 == 0x07) { + u32 sum1; + u32 sum2; + u32 sum3; + u32 sum4; + + // UHADD8 + if (op2 == 0x04) { + sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); + } + // UHSUB8 + else { + sum1 = (rn_val & 0xFF) - (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); + } + + sum1 >>= 1; + sum2 >>= 1; + sum3 >>= 1; + sum4 >>= 1; + + state->Reg[rd_idx] = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24); + return 1; + } + } + break; + case 0x68: + { + u32 rd = (instr >> 12) & 0xF; + u32 rn = (instr >> 16) & 0xF; + u32 rm = (instr >> 0) & 0xF; + u32 from = state->Reg[rn]; + u32 to = state->Reg[rm]; + u32 cpsr = ARMul_GetCPSR(state); + if ((instr & 0xFF0) == 0xFB0) { // SEL + u32 result; + if (cpsr & (1 << 16)) + result = from & 0xff; + else + result = to & 0xff; + if (cpsr & (1 << 17)) + result |= from & 0x0000ff00; + else + result |= to & 0x0000ff00; + if (cpsr & (1 << 18)) + result |= from & 0x00ff0000; + else + result |= to & 0x00ff0000; + if (cpsr & (1 << 19)) + result |= from & 0xff000000; + else + result |= to & 0xff000000; + state->Reg[rd] = result; + return 1; + } + } + printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); + break; + + case 0x6a: // SSAT, SSAT16, SXTB, and SXTAB + { + const u8 op2 = BITS(5, 7); + + // SSAT16 + if (op2 == 0x01) { + const u8 rd_idx = BITS(12, 15); + const u8 rn_idx = BITS(0, 3); + const u8 num_bits = BITS(16, 19) + 1; + const s16 min = -(0x8000 >> (16 - num_bits)); + const s16 max = (0x7FFF >> (16 - num_bits)); + s16 rn_lo = (state->Reg[rn_idx]); + s16 rn_hi = (state->Reg[rn_idx] >> 16); + + if (rn_lo > max) { + rn_lo = max; + SETQ; + } else if (rn_lo < min) { + rn_lo = min; + SETQ; + } + + if (rn_hi > max) { + rn_hi = max; + SETQ; + } else if (rn_hi < min) { + rn_hi = min; + SETQ; + } + + state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16); + return 1; + } + else if (op2 == 0x03) { + const u8 rotation = BITS(10, 11) * 8; + u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF); + if (rm & 0x80) + rm |= 0xffffff00; + + // SXTB, otherwise SXTAB + if (BITS(16, 19) == 0xf) + state->Reg[BITS(12, 15)] = rm; + else + state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm; + + return 1; + } + else { + printf("Unimplemented op: SSAT"); + } + } + break; + + case 0x6b: // REV, REV16, SXTH, and SXTAH + { + const u8 op2 = BITS(5, 7); + + // REV + if (op2 == 0x01) { + DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); + return 1; + } + // REV16 + else if (op2 == 0x05) { + DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); + return 1; + } + else if (op2 == 0x03) { + const u8 rotate = BITS(10, 11) * 8; + + u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF); + if (rm & 0x8000) + rm |= 0xffff0000; + + // SXTH, otherwise SXTAH + if (BITS(16, 19) == 15) + state->Reg[BITS(12, 15)] = rm; + else + state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm; + + return 1; + } + } + break; + + case 0x6c: // UXTB16 and UXTAB16 + { + const u8 rm_idx = BITS(0, 3); + const u8 rn_idx = BITS(16, 19); + const u8 rd_idx = BITS(12, 15); + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + const u32 rotation = BITS(10, 11) * 8; + const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); + + // UXTB16 + if ((instr & 0xf03f0) == 0xf0070) { + state->Reg[rd_idx] = rotated_rm & 0x00FF00FF; + } + else { // UXTAB16 + const u8 lo_rotated = (rotated_rm & 0xFF); + const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated; + + const u8 hi_rotated = (rotated_rm >> 16) & 0xFF; + const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated; + + state->Reg[rd_idx] = ((hi_result << 16) | (lo_result & 0xFFFF)); + } + + return 1; + } + break; + case 0x6e: // USAT, USAT16, UXTB, and UXTAB + { + const u8 op2 = BITS(5, 7); + + // USAT16 + if (op2 == 0x01) { + const u8 rd_idx = BITS(12, 15); + const u8 rn_idx = BITS(0, 3); + const u8 num_bits = BITS(16, 19); + const s16 max = 0xFFFF >> (16 - num_bits); + s16 rn_lo = (state->Reg[rn_idx]); + s16 rn_hi = (state->Reg[rn_idx] >> 16); + + if (max < rn_lo) { + rn_lo = max; + SETQ; + } else if (rn_lo < 0) { + rn_lo = 0; + SETQ; + } + + if (max < rn_hi) { + rn_hi = max; + SETQ; + } else if (rn_hi < 0) { + rn_hi = 0; + SETQ; + } + + state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF); + return 1; + } + else if (op2 == 0x03) { + const u8 rotate = BITS(10, 11) * 8; + const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF); + + if (BITS(16, 19) == 0xf) + /* UXTB */ + state->Reg[BITS(12, 15)] = rm; + else + /* UXTAB */ + state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm; + + return 1; + } + else { + printf("Unimplemented op: USAT"); + } + } + break; + + case 0x6f: // UXTH, UXTAH, and REVSH. + { + const u8 op2 = BITS(5, 7); + + // REVSH + if (op2 == 0x05) { + DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8); + if (DEST & 0x8000) + DEST |= 0xffff0000; + return 1; + } + // UXTH and UXTAH + else if (op2 == 0x03) { + const u8 rotate = BITS(10, 11) * 8; + const ARMword rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF); + + // UXTH + if (BITS(16, 19) == 0xf) { + state->Reg[BITS(12, 15)] = rm; + } + // UXTAH + else { + state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm; + } + + return 1; + } + } + case 0x70: + // ichfly + // SMUAD, SMUSD, SMLAD, and SMLSD + if ((instr & 0xf0d0) == 0xf010 || (instr & 0xf0d0) == 0xf050 || + (instr & 0xd0) == 0x10 || (instr & 0xd0) == 0x50) + { + const u8 rd_idx = BITS(16, 19); + const u8 rn_idx = BITS(0, 3); + const u8 rm_idx = BITS(8, 11); + const u8 ra_idx = BITS(12, 15); + const bool do_swap = (BIT(5) == 1); + + u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + if (do_swap) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + + const s16 rm_lo = (rm_val & 0xFFFF); + const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); + const s16 rn_lo = (rn_val & 0xFFFF); + const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); + + const u32 product1 = (rn_lo * rm_lo); + const u32 product2 = (rn_hi * rm_hi); + + // SMUAD and SMLAD + if (BIT(6) == 0) { + state->Reg[rd_idx] = product1 + product2; + + if (BITS(12, 15) != 15) { + state->Reg[rd_idx] += state->Reg[ra_idx]; + if (ARMul_AddOverflowQ(product1 + product2, state->Reg[ra_idx])) + SETQ; + } + + if (ARMul_AddOverflowQ(product1, product2)) + SETQ; + } + // SMUSD and SMLSD + else { + state->Reg[rd_idx] = product1 - product2; + + if (BITS(12, 15) != 15) { + state->Reg[rd_idx] += state->Reg[ra_idx]; + + if (ARMul_AddOverflowQ(product1 - product2, state->Reg[ra_idx])) + SETQ; + } + } + + return 1; + } + break; + case 0x74: // SMLALD and SMLSLD + { + const u8 rm_idx = BITS(8, 11); + const u8 rn_idx = BITS(0, 3); + const u8 rdlo_idx = BITS(12, 15); + const u8 rdhi_idx = BITS(16, 19); + const bool do_swap = (BIT(5) == 1); + + const u32 rdlo_val = state->Reg[rdlo_idx]; + const u32 rdhi_val = state->Reg[rdhi_idx]; + const u32 rn_val = state->Reg[rn_idx]; + u32 rm_val = state->Reg[rm_idx]; + + if (do_swap) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + + const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF); + const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF); + s64 result; + + // SMLALD + if (BIT(6) == 0) { + result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); + } + // SMLSLD + else { + result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); + } + + state->Reg[rdlo_idx] = (result & 0xFFFFFFFF); + state->Reg[rdhi_idx] = ((result >> 32) & 0xFFFFFFFF); + return 1; + } + break; + case 0x75: // SMMLA, SMMUL, and SMMLS + { + const u8 rm_idx = BITS(8, 11); + const u8 rn_idx = BITS(0, 3); + const u8 ra_idx = BITS(12, 15); + const u8 rd_idx = BITS(16, 19); + const bool do_round = (BIT(5) == 1); + + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + // Assume SMMUL by default. + s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val; + + if (ra_idx != 15) { + const u32 ra_val = state->Reg[ra_idx]; + + // SMMLA, otherwise SMMLS + if (BIT(6) == 0) + result += ((s64)ra_val << 32); + else + result = ((s64)ra_val << 32) - result; + } + + if (do_round) + result += 0x80000000; + + state->Reg[rd_idx] = ((result >> 32) & 0xFFFFFFFF); + return 1; + } + break; + case 0x78: + if (BITS(20, 24) == 0x18) + { + const u8 rm_idx = BITS(8, 11); + const u8 rn_idx = BITS(0, 3); + const u8 rd_idx = BITS(16, 19); + + const u32 rm_val = state->Reg[rm_idx]; + const u32 rn_val = state->Reg[rn_idx]; + + const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF); + const u8 diff2 = ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF); + const u8 diff3 = ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF); + const u8 diff4 = ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF); + + u32 finalDif = (diff1 + diff2 + diff3 + diff4); + + // Op is USADA8 if true. + const u8 ra_idx = BITS(12, 15); + if (ra_idx != 15) + finalDif += state->Reg[ra_idx]; + + state->Reg[rd_idx] = finalDif; + return 1; + } + break; + case 0x7a: + printf ("Unhandled v6 insn: usbfx\n"); + break; + case 0x7c: + printf ("Unhandled v6 insn: bfc/bfi\n"); + break; + case 0x84: + printf ("Unhandled v6 insn: srs\n"); + break; + default: + break; + } + printf("Unhandled v6 insn: UNKNOWN: %08x %08X\n", instr, BITS(20, 27)); + return 0; + } diff --git a/source/arm/interpreter/arminit.cpp b/source/arm/interpreter/arminit.cpp new file mode 100644 index 0000000..97b866b --- /dev/null +++ b/source/arm/interpreter/arminit.cpp @@ -0,0 +1,528 @@ +/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +//#include + +#include "Kernel.h" + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" + +/***************************************************************************\ +* Definitions for the emulator architecture * +\***************************************************************************/ + +void ARMul_EmulateInit (void); +ARMul_State *ARMul_NewState (ARMul_State * state); +void ARMul_Reset (ARMul_State * state); +ARMword ARMul_DoCycle (ARMul_State * state); +unsigned ARMul_DoCoPro (ARMul_State * state); +ARMword ARMul_DoProg (ARMul_State * state); +ARMword ARMul_DoInstr (ARMul_State * state); +void ARMul_Abort (ARMul_State * state, ARMword address); + +unsigned ARMul_MultTable[32] = { + 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, + 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 +}; +ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ +char ARMul_BitList[256]; /* number of bits in a byte table */ + +//chy 2006-02-22 add test debugmode +extern int debugmode; +extern int remote_interrupt( void ); + + +void arm_dyncom_Abort(ARMul_State * state, ARMword vector) +{ + ARMul_Abort(state, vector); +} + + +/* ahe-ykl : the following code to initialize user mode + code is architecture dependent and probably model dependant. */ + +/*#include "skyeye_arch.h" +#include "skyeye_pref.h" +#include "skyeye_exec_info.h" +#include "bank_defs.h"*/ +//#include "armcpu.h" +//#include "skyeye_callback.h" + +/* + ARM_CPU_State* cpu = get_current_cpu(); + arm_core_t* core = &cpu->core[0]; + + uint32_t sp = info->initial_sp; + + core->Cpsr = 0x10; // User mode +// FIXME: may need to add thumb +core->Reg[13] = sp; +core->Reg[10] = info->start_data; +core->Reg[0] = 0; +bus_read(32, sp + 4, &(core->Reg[1])); +bus_read(32, sp + 8, &(core->Reg[2])); +*/ +/***************************************************************************\ +* Call this routine once to set up the emulator's tables. * +\***************************************************************************/ + +void +ARMul_EmulateInit (void) +{ + unsigned int i, j; + + for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */ + ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); + } + + for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ + for (j = 1; j < 256; j <<= 1) + for (i = 0; i < 256; i++) + if ((i & j) > 0) + ARMul_BitList[i]++; + + for (i = 0; i < 256; i++) + ARMul_BitList[i] *= 4; /* you always need 4 times these values */ + +} + +/***************************************************************************\ +* Returns a new instantiation of the ARMulator's state * +\***************************************************************************/ + +ARMul_State * +ARMul_NewState (ARMul_State *state) +{ + unsigned i, j; + + memset (state, 0, sizeof (ARMul_State)); + + state->Emulate = RUN; + for (i = 0; i < 16; i++) { + state->Reg[i] = 0; + for (j = 0; j < 7; j++) + state->RegBank[j][i] = 0; + } + for (i = 0; i < 7; i++) + state->Spsr[i] = 0; + state->Mode = 0; + + state->CallDebug = FALSE; + state->Debug = FALSE; + state->VectorCatch = 0; + state->Aborted = FALSE; + state->Reseted = FALSE; + state->Inted = 3; + state->LastInted = 3; + + state->CommandLine = NULL; + + state->EventSet = 0; + state->Now = 0; + state->EventPtr = + (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * + sizeof (struct EventNode *)); +#if DIFF_STATE + state->state_log = fopen("/data/state.log", "w"); + printf("create pc log file.\n"); +#endif + if (state->EventPtr == NULL) { + printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n"); + exit(-1); + //skyeye_exit (-1); + } + for (i = 0; i < EVENTLISTSIZE; i++) + *(state->EventPtr + i) = NULL; +#if SAVE_LOG + state->state_log = fopen("/tmp/state.log", "w"); + printf("create pc log file.\n"); +#else +#if DIFF_LOG + state->state_log = fopen("/tmp/state.log", "r"); + printf("loaded pc log file.\n"); +#endif +#endif + +#ifdef ARM61 + state->prog32Sig = LOW; + state->data32Sig = LOW; +#else + state->prog32Sig = HIGH; + state->data32Sig = HIGH; +#endif + + state->lateabtSig = HIGH; + state->bigendSig = LOW; + + //chy:2003-08-19 + state->LastTime = 0; + state->CP14R0_CCD = -1; + + /* ahe-ykl: common function for interpret and dyncom */ + /*sky_pref_t *pref = get_skyeye_pref(); + if (pref->user_mode_sim) + register_callback(arm_user_mode_init, Bootmach_callback); + */ + + memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128); + state->exclusive_access_state = 0; + //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t)); + //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t)); + return (state); +} + +/***************************************************************************\ +* Call this routine to set ARMulator to model a certain processor * +\***************************************************************************/ + +void +ARMul_SelectProcessor (ARMul_State * state, unsigned properties) +{ + if (properties & ARM_Fix26_Prop) { + state->prog32Sig = LOW; + state->data32Sig = LOW; + } else { + state->prog32Sig = HIGH; + state->data32Sig = HIGH; + } + /* 2004-05-09 chy + below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function + */ + // state->lateabtSig = HIGH; + + + state->is_v4 = + (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; + state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; + state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; + state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; + state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; + /* state->is_v6 = LOW */; + /* jeff.du 2010-08-05 */ + state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; + state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; + //chy 2005-09-19 + state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW; + + /* shenoubang 2012-3-11 */ + state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW; + + /* Only initialse the coprocessor support once we + know what kind of chip we are dealing with. */ + //ARMul_CoProInit (state); + +} + +/***************************************************************************\ +* Call this routine to set up the initial machine state (or perform a RESET * +\***************************************************************************/ + +void +ARMul_Reset (ARMul_State * state) +{ + //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + state->NextInstr = 0; + if (state->prog32Sig) { + state->Reg[15] = 0; + state->Cpsr = INTBITS | SVC32MODE; + state->Mode = SVC32MODE; + } else { + state->Reg[15] = R15INTBITS | SVC26MODE; + state->Cpsr = INTBITS | SVC26MODE; + state->Mode = SVC26MODE; + } + //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + //ARMul_CPSRAltered (state); + state->Bank = SVCBANK; + FLUSHPIPE; + + state->EndCondition = 0; + state->ErrorCode = 0; + + //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + state->NresetSig = HIGH; + state->NfiqSig = HIGH; + state->NirqSig = HIGH; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + state->abortSig = LOW; + state->AbortAddr = 1; + + state->NumInstrs = 0; + state->NumNcycles = 0; + state->NumScycles = 0; + state->NumIcycles = 0; + state->NumCcycles = 0; + state->NumFcycles = 0; + + //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + //mmu_reset (state); + //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + + //mem_reset (state); /* move to memory/ram.c */ + + //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); + /*remove later. walimis 03.7.17 */ + //io_reset(state); + //lcd_disable(state); + + /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will + *be configured in skyeye_option_init and it is called after ARMul_NewState*/ + state->tea_break_ok = 0; + state->tea_break_addr = 0; + state->tea_pc = 0; +#ifdef DBCT + if (!skyeye_config.no_dbct) { + //teawater add for arm2x86 2005.02.14------------------------------------------- + if (arm2x86_init (state)) { + printf ("SKYEYE: arm2x86_init error\n"); + //skyeye_exit (-1); + } + //AJ2D-------------------------------------------------------------------------- + } +#endif +} + + +/***************************************************************************\ +* Emulate the execution of an entire program. Start the correct emulator * +* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * +* address of the last instruction that is executed. * +\***************************************************************************/ + +//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- +#ifdef DBCT_TEST_SPEED +static ARMul_State *dbct_test_speed_state = NULL; +static void +dbct_test_speed_sig(int signo) +{ + printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count); + exit(0); + //skyeye_exit(0); +} +#endif //DBCT_TEST_SPEED +//AJ2D-------------------------------------------------------------------------- + +ARMword +ARMul_DoProg (ARMul_State * state) +{ + ARMword pc = 0; + + /* + * 2007-01-24 removed the term-io functions by Anthony Lee, + * moved to "device/uart/skyeye_uart_stdio.c". + */ + +//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- +#ifdef DBCT_TEST_SPEED + { + if (!dbct_test_speed_state) { + //init timer + struct itimerval value; + struct sigaction act; + + dbct_test_speed_state = state; + state->instr_count = 0; + act.sa_handler = dbct_test_speed_sig; + act.sa_flags = SA_RESTART; + //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF +#ifndef __CYGWIN__ + if (sigaction(SIGVTALRM, &act, NULL) == -1) { +#else + if (sigaction(SIGALRM, &act, NULL) == -1) { +#endif //__CYGWIN__ + fprintf(stderr, "init timer error.\n"); + exit(-1); + //skyeye_exit(-1); + } + if (skyeye_config.dbct_test_speed_sec) { + value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec; + } else { + value.it_value.tv_sec = DBCT_TEST_SPEED_SEC; + } + printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec); + value.it_value.tv_usec = 0; + value.it_interval.tv_sec = 0; + value.it_interval.tv_usec = 0; +#ifndef __CYGWIN__ + if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) { +#else + if (setitimer(ITIMER_REAL, &value, NULL) == -1) { +#endif //__CYGWIN__ + fprintf(stderr, "init timer error.\n"); + //skyeye_exit(-1); + } + } + } +#endif //DBCT_TEST_SPEED +//AJ2D-------------------------------------------------------------------------- + state->Emulate = RUN; + while (state->Emulate != STOP) { + state->Emulate = RUN; + + /*ywc 2005-03-31 */ + if (state->prog32Sig && ARMul_MODE32BIT) { +#ifdef DBCT + if (skyeye_config.no_dbct) { + pc = ARMul_Emulate32 (state); + } else { + pc = ARMul_Emulate32_dbct (state); + } +#else + pc = ARMul_Emulate32 (state); +#endif + } + + else { + //pc = ARMul_Emulate26 (state); + } + //chy 2006-02-22, should test debugmode first + //chy 2006-04-14, put below codes in ARMul_Emulate +#if 0 + if(debugmode) + if(remote_interrupt()) + state->Emulate = STOP; +#endif + } + + /* + * 2007-01-24 removed the term-io functions by Anthony Lee, + * moved to "device/uart/skyeye_uart_stdio.c". + */ + + return (pc); +} + +/***************************************************************************\ +* Emulate the execution of one instruction. Start the correct emulator * +* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * +* address of the instruction that is executed. * +\***************************************************************************/ + +ARMword +ARMul_DoInstr (ARMul_State * state) +{ + ARMword pc = 0; + + state->Emulate = ONCE; + + /*ywc 2005-03-31 */ + if (state->prog32Sig && ARMul_MODE32BIT) { +#ifdef DBCT + if (skyeye_config.no_dbct) { + pc = ARMul_Emulate32 (state); + } else { +//teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- +#ifndef DBCT_GDBRSP + printf("DBCT GDBRSP function switch is off.\n"); + printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n"); + skyeye_exit(-1); +#endif //DBCT_GDBRSP +//AJ2D-------------------------------------------------------------------------- + pc = ARMul_Emulate32_dbct (state); + } +#else + pc = ARMul_Emulate32 (state); +#endif + } + + //else + //pc = ARMul_Emulate26 (state); + + return (pc); +} + +/***************************************************************************\ +* This routine causes an Abort to occur, including selecting the correct * +* mode, register bank, and the saving of registers. Call with the * +* appropriate vector's memory address (0,4,8 ....) * +\***************************************************************************/ + +void +ARMul_Abort (ARMul_State * state, ARMword vector) +{ + ARMword temp; + int isize = INSN_SIZE; + int esize = (TFLAG ? 0 : 4); + int e2size = (TFLAG ? -4 : 0); + + state->Aborted = FALSE; + + if (state->prog32Sig) + if (ARMul_MODE26BIT) + temp = R15PC; + else + temp = state->Reg[15]; + else + temp = R15PC | ECC | ER15INT | EMODE; + + switch (vector) { + case ARMul_ResetV: /* RESET */ + SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, + 0); + break; + case ARMul_UndefinedInstrV: /* Undefined Instruction */ + SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, + isize); + break; + case ARMul_SWIV: /* Software Interrupt */ + SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, + isize); + break; + case ARMul_PrefetchAbortV: /* Prefetch Abort */ + state->AbortAddr = 1; + SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, + esize); + break; + case ARMul_DataAbortV: /* Data Abort */ + SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, + e2size); + break; + case ARMul_AddrExceptnV: /* Address Exception */ + SETABORT (IBIT, SVC26MODE, isize); + break; + case ARMul_IRQV: /* IRQ */ + //chy 2003-09-02 the if sentence seems no use +#if 0 + if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) + || (temp & ARMul_CP13_R0_IRQ)) +#endif + SETABORT (IBIT, + state->prog32Sig ? IRQ32MODE : IRQ26MODE, + esize); + break; + case ARMul_FIQV: /* FIQ */ + //chy 2003-09-02 the if sentence seems no use +#if 0 + if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) + || (temp & ARMul_CP13_R0_FIQ)) +#endif + SETABORT (INTBITS, + state->prog32Sig ? FIQ32MODE : FIQ26MODE, + esize); + break; + } + + if (ARMul_MODE32BIT) { + /*if (state->mmu.control & CONTROL_VECTOR) + vector += 0xffff0000; //for v4 high exception address*/ + if (state->vector_remap_flag) + vector += state->vector_remap_addr; /* support some remap function in LPC processor */ + ARMul_SetR15 (state, vector); + } else + ARMul_SetR15 (state, R15CCINTMODE | vector); +} diff --git a/source/arm/interpreter/armsupp.cpp b/source/arm/interpreter/armsupp.cpp new file mode 100644 index 0000000..634718c --- /dev/null +++ b/source/arm/interpreter/armsupp.cpp @@ -0,0 +1,1145 @@ +/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "Kernel.h" + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" +#include "arm/disassembler/arm_disasm.h" +#include "arm/memory.h" + + +static ARMword ModeToBank (ARMword); +static void EnvokeList (ARMul_State *, unsigned int, unsigned int); + +struct EventNode { + /* An event list node. */ + unsigned (*func) (ARMul_State *); /* The function to call. */ + struct EventNode *next; +}; + +/* This routine returns the value of a register from a mode. */ + +ARMword +ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg) +{ + mode &= MODEBITS; + if (mode != state->Mode) + return (state->RegBank[ModeToBank ((ARMword) mode)][reg]); + else + return (state->Reg[reg]); +} + +/* This routine sets the value of a register for a mode. */ + +void +ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value) +{ + mode &= MODEBITS; + if (mode != state->Mode) + state->RegBank[ModeToBank ((ARMword) mode)][reg] = value; + else + state->Reg[reg] = value; +} + +/* This routine returns the value of the PC, mode independently. */ + +ARMword +ARMul_GetPC (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return state->Reg[15]; + else + return R15PC; +} + +/* This routine returns the value of the PC, mode independently. */ + +ARMword +ARMul_GetNextPC (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return state->Reg[15] + INSN_SIZE; + else + return (state->Reg[15] + INSN_SIZE) & R15PCBITS; +} + +/* This routine sets the value of the PC. */ + +void +ARMul_SetPC (ARMul_State * state, ARMword value) +{ + if (ARMul_MODE32BIT) + state->Reg[15] = value & PCBITS; + else + state->Reg[15] = R15CCINTMODE | (value & R15PCBITS); + FLUSHPIPE; +} + +/* This routine returns the value of register 15, mode independently. */ + +ARMword +ARMul_GetR15 (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return (state->Reg[15]); + else + return (R15PC | ECC | ER15INT | EMODE); +} + +/* This routine sets the value of Register 15. */ + +void +ARMul_SetR15 (ARMul_State * state, ARMword value) +{ + if (ARMul_MODE32BIT) + state->Reg[15] = value & PCBITS; + else { + state->Reg[15] = value; + ARMul_R15Altered (state); + } + FLUSHPIPE; +} + +/* This routine returns the value of the CPSR. */ + +ARMword +ARMul_GetCPSR (ARMul_State * state) +{ + //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator + //return (CPSR | state->Cpsr); for gdb20030716 + return (CPSR); //had be tested in old skyeye with gdb5.0-5.3 +} + +/* This routine sets the value of the CPSR. */ + +void +ARMul_SetCPSR (ARMul_State * state, ARMword value) +{ + state->Cpsr = value; + ARMul_CPSRAltered (state); +} + +/* This routine does all the nasty bits involved in a write to the CPSR, + including updating the register bank, given a MSR instruction. */ + +void +ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) +{ + state->Cpsr = ARMul_GetCPSR (state); + //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode + if (state->Mode != USER26MODE && state->Mode != USER32MODE ) { + /* In user mode, only write flags. */ + if (BIT (16)) + SETPSR_C (state->Cpsr, rhs); + if (BIT (17)) + SETPSR_X (state->Cpsr, rhs); + if (BIT (18)) + SETPSR_S (state->Cpsr, rhs); + } + if (BIT (19)) + SETPSR_F (state->Cpsr, rhs); + ARMul_CPSRAltered (state); +} + +/* Get an SPSR from the specified mode. */ + +ARMword +ARMul_GetSPSR (ARMul_State * state, ARMword mode) +{ + ARMword bank = ModeToBank (mode & MODEBITS); + + if (!BANK_CAN_ACCESS_SPSR (bank)) + return ARMul_GetCPSR (state); + + return state->Spsr[bank]; +} + +/* This routine does a write to an SPSR. */ + +void +ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) +{ + ARMword bank = ModeToBank (mode & MODEBITS); + + if (BANK_CAN_ACCESS_SPSR (bank)) + state->Spsr[bank] = value; +} + +/* This routine does a write to the current SPSR, given an MSR instruction. */ + +void +ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs) +{ + if (BANK_CAN_ACCESS_SPSR (state->Bank)) { + if (BIT (16)) + SETPSR_C (state->Spsr[state->Bank], rhs); + if (BIT (17)) + SETPSR_X (state->Spsr[state->Bank], rhs); + if (BIT (18)) + SETPSR_S (state->Spsr[state->Bank], rhs); + if (BIT (19)) + SETPSR_F (state->Spsr[state->Bank], rhs); + } +} + +/* This routine updates the state of the emulator after the Cpsr has been + changed. Both the processor flags and register bank are updated. */ + +void +ARMul_CPSRAltered (ARMul_State * state) +{ + ARMword oldmode; + + if (state->prog32Sig == LOW) + state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS); + + oldmode = state->Mode; + + /*if (state->Mode != (state->Cpsr & MODEBITS)) { + state->Mode = + ARMul_SwitchMode (state, state->Mode, + state->Cpsr & MODEBITS); + + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + }*/ + //state->Cpsr &= ~MODEBITS; + + ASSIGNINT (state->Cpsr & INTBITS); + //state->Cpsr &= ~INTBITS; + ASSIGNN ((state->Cpsr & NBIT) != 0); + //state->Cpsr &= ~NBIT; + ASSIGNZ ((state->Cpsr & ZBIT) != 0); + //state->Cpsr &= ~ZBIT; + ASSIGNC ((state->Cpsr & CBIT) != 0); + //state->Cpsr &= ~CBIT; + ASSIGNV ((state->Cpsr & VBIT) != 0); + //state->Cpsr &= ~VBIT; + ASSIGNQ ((state->Cpsr & QBIT) != 0); + //state->Cpsr &= ~QBIT; + state->GEFlag = (state->Cpsr & 0x000F0000); +#ifdef MODET + ASSIGNT ((state->Cpsr & TBIT) != 0); + //state->Cpsr &= ~TBIT; +#endif + + if (oldmode > SVC26MODE) { + if (state->Mode <= SVC26MODE) { + state->Emulate = CHANGEMODE; + state->Reg[15] = ECC | ER15INT | EMODE | R15PC; + } + } else { + if (state->Mode > SVC26MODE) { + state->Emulate = CHANGEMODE; + state->Reg[15] = R15PC; + } else + state->Reg[15] = ECC | ER15INT | EMODE | R15PC; + } +} + +/* This routine updates the state of the emulator after register 15 has + been changed. Both the processor flags and register bank are updated. + This routine should only be called from a 26 bit mode. */ + +void +ARMul_R15Altered (ARMul_State * state) +{ + if (state->Mode != R15MODE) { + state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE); + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + } + + if (state->Mode > SVC26MODE) + state->Emulate = CHANGEMODE; + + ASSIGNR15INT (R15INT); + + ASSIGNN ((state->Reg[15] & NBIT) != 0); + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); + ASSIGNC ((state->Reg[15] & CBIT) != 0); + ASSIGNV ((state->Reg[15] & VBIT) != 0); +} + +/* This routine controls the saving and restoring of registers across mode + changes. The regbank matrix is largely unused, only rows 13 and 14 are + used across all modes, 8 to 14 are used for FIQ, all others use the USER + column. It's easier this way. old and new parameter are modes numbers. + Notice the side effect of changing the Bank variable. */ + +ARMword +ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode) +{ + unsigned i; + ARMword oldbank; + ARMword newbank; + static int revision_value = 53; + + oldbank = ModeToBank (oldmode); + newbank = state->Bank = ModeToBank (newmode); + + /* Do we really need to do it? */ + if (oldbank != newbank) { + if (oldbank == 3 && newbank == 2) { + //printf("icounter is %d PC is %x MODE CHANGED : %d --> %d\n", state->NumInstrs, state->pc, oldbank, newbank); + if (state->NumInstrs >= 5832487) { +// printf("%d, ", state->NumInstrs + revision_value); +// printf("revision_value : %d\n", revision_value); + revision_value ++; + } + } + /* Save away the old registers. */ + switch (oldbank) { + case USERBANK: + case IRQBANK: + case SVCBANK: + case ABORTBANK: + case UNDEFBANK: + if (newbank == FIQBANK) + for (i = 8; i < 13; i++) + state->RegBank[USERBANK][i] = + state->Reg[i]; + state->RegBank[oldbank][13] = state->Reg[13]; + state->RegBank[oldbank][14] = state->Reg[14]; + break; + case FIQBANK: + for (i = 8; i < 15; i++) + state->RegBank[FIQBANK][i] = state->Reg[i]; + break; + case DUMMYBANK: + for (i = 8; i < 15; i++) + state->RegBank[DUMMYBANK][i] = 0; + break; + default: + abort (); + } + + /* Restore the new registers. */ + switch (newbank) { + case USERBANK: + case IRQBANK: + case SVCBANK: + case ABORTBANK: + case UNDEFBANK: + if (oldbank == FIQBANK) + for (i = 8; i < 13; i++) + state->Reg[i] = + state->RegBank[USERBANK][i]; + state->Reg[13] = state->RegBank[newbank][13]; + state->Reg[14] = state->RegBank[newbank][14]; + break; + case FIQBANK: + for (i = 8; i < 15; i++) + state->Reg[i] = state->RegBank[FIQBANK][i]; + break; + case DUMMYBANK: + for (i = 8; i < 15; i++) + state->Reg[i] = 0; + break; + default: + abort (); + } + } + + return newmode; +} + +/* Given a processor mode, this routine returns the + register bank that will be accessed in that mode. */ + +static ARMword +ModeToBank (ARMword mode) +{ + static ARMword bankofmode[] = { + USERBANK, FIQBANK, IRQBANK, SVCBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + USERBANK, FIQBANK, IRQBANK, SVCBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK + }; + + if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0]))) + return DUMMYBANK; + + return bankofmode[mode]; +} + +/* Returns the register number of the nth register in a reg list. */ + +unsigned +ARMul_NthReg (ARMword instr, unsigned number) +{ + unsigned bit, upto; + + for (bit = 0, upto = 0; upto <= number; bit++) + if (BIT (bit)) + upto++; + + return (bit - 1); +} + +/* Unsigned sum of absolute difference */ +u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) +{ + if (left > right) + return left - right; + + return right - left; +} + +/* Assigns the N and Z flags depending on the value of result. */ + +void +ARMul_NegZero (ARMul_State * state, ARMword result) +{ + if (NEG (result)) { + SETN; + CLEARZ; + } else if (result == 0) { + CLEARN; + SETZ; + } else { + CLEARN; + CLEARZ; + } +} + +// Add with carry, indicates if a carry-out or signed overflow occurred. +u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bool* overflow_occurred) +{ + u64 unsigned_sum = (u64)left + (u64)right + (u64)carry_in; + s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)carry_in; + u64 result = (unsigned_sum & 0xFFFFFFFF); + + if (carry_out_occurred) + *carry_out_occurred = (result != unsigned_sum); + + if (overflow_occurred) + *overflow_occurred = ((s64)(s32)result != signed_sum); + + return (u32)result; +} + +// Compute whether an addition of A and B, giving RESULT, overflowed. +bool AddOverflow(ARMword a, ARMword b, ARMword result) +{ + return ((NEG(a) && NEG(b) && POS(result)) || + (POS(a) && POS(b) && NEG(result))); +} + +// Compute whether a subtraction of A and B, giving RESULT, overflowed. +bool SubOverflow(ARMword a, ARMword b, ARMword result) +{ + return ((NEG(a) && POS(b) && POS(result)) || + (POS(a) && NEG(b) && NEG(result))); +} + +/* Assigns the C flag after an addition of a and b to give result. */ + +void +ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNC ((NEG (a) && NEG (b)) || + (NEG (a) && POS (result)) || (NEG (b) && POS (result))); +} + +/* Assigns the V flag after an addition of a and b to give result. */ + +void +ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNV (AddOverflow (a, b, result)); +} + +// Returns true if the Q flag should be set as a result of overflow. +bool ARMul_AddOverflowQ(ARMword a, ARMword b) +{ + u32 result = a + b; + if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0) + return true; + + return false; +} + +/* Assigns the C flag after an subtraction of a and b to give result. */ + +void +ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNC ((NEG (a) && POS (b)) || + (NEG (a) && POS (result)) || (POS (b) && POS (result))); +} + +/* Assigns the V flag after an subtraction of a and b to give result. */ + +void +ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNV (SubOverflow (a, b, result)); +} + +/* 8-bit signed saturated addition */ +u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right) +{ + u8 result = left + right; + + if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) == 0) { + if (left & 0x80) + result = 0x80; + else + result = 0x7F; + } + + return result; +} + +/* 8-bit signed saturated subtraction */ +u8 ARMul_SignedSaturatedSub8(u8 left, u8 right) +{ + u8 result = left - right; + + if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) != 0) { + if (left & 0x80) + result = 0x80; + else + result = 0x7F; + } + + return result; +} + +/* 16-bit signed saturated addition */ +u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right) +{ + u16 result = left + right; + + if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) == 0) { + if (left & 0x8000) + result = 0x8000; + else + result = 0x7FFF; + } + + return result; +} + +/* 16-bit signed saturated subtraction */ +u16 ARMul_SignedSaturatedSub16(u16 left, u16 right) +{ + u16 result = left - right; + + if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) != 0) { + if (left & 0x8000) + result = 0x8000; + else + result = 0x7FFF; + } + + return result; +} + +/* 8-bit unsigned saturated addition */ +u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right) +{ + u8 result = left + right; + + if (result < left) + result = 0xFF; + + return result; +} + +/* 16-bit unsigned saturated addition */ +u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right) +{ + u16 result = left + right; + + if (result < left) + result = 0xFFFF; + + return result; +} + +/* 8-bit unsigned saturated subtraction */ +u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right) +{ + if (left <= right) + return 0; + + return left - right; +} + +/* 16-bit unsigned saturated subtraction */ +u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right) +{ + if (left <= right) + return 0; + + return left - right; +} + +// Signed saturation. +u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred) +{ + const u32 max = (1 << shift) - 1; + const s32 top = (value >> shift); + + if (top > 0) { + *saturation_occurred = true; + return max; + } + else if (top < -1) { + *saturation_occurred = true; + return ~max; + } + + *saturation_occurred = false; + return (u32)value; +} + +// Unsigned saturation +u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred) +{ + const u32 max = (1 << shift) - 1; + + if (value < 0) { + *saturation_occurred = true; + return 0; + } else if ((u32)value > max) { + *saturation_occurred = true; + return max; + } + + *saturation_occurred = false; + return (u32)value; +} + +/* This function does the work of generating the addresses used in an + LDC instruction. The code here is always post-indexed, it's up to the + caller to get the input address correct and to handle base register + modification. It also handles the Busy-Waiting. */ + +void +ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address) +{ + unsigned cpab; + ARMword data; + + UNDEF_LSCPCBaseWb; + //printf("SKYEYE ARMul_LDC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); + /*chy 2004-05-23 should update this function in the future,should concern dataabort*/ +// chy 2004-05-25 , fix it now,so needn't printf +// printf("SKYEYE ARMul_LDC, should update this function!!!!!\n"); + //exit(-1); + + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->LDC[CPNum]) { + /* + printf + ("SKYEYE ARMul_LDC,NOT ALLOW, underinstr, CPnum is %x, instr %x, addr %x\n", + CPNum, instr, address); + */ + ARMul_UndefInstr (state, instr); + return; + } + + /*if (ADDREXCEPT (address)) + INTERNALABORT (address);*/ + + cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0); + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + + if (IntPending (state)) { + cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, + instr, 0); + return; + } else + cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, + 0); + } + if (cpab == ARMul_CANT) { + /* + printf + ("SKYEYE ARMul_LDC,NOT CAN, underinstr, CPnum is %x, instr %x, addr %x\n", + CPNum, instr, address); + */ + CPTAKEABORT; + return; + } + + cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0); + data = ARMul_LoadWordN (state, address); + //chy 2004-05-25 + if (state->abortSig || state->Aborted) + goto L_ldc_takeabort; + + BUSUSEDINCPCN; +//chy 2004-05-25 + /* + if (BIT (21)) + LSBase = state->Base; + */ + + cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); + + while (cpab == ARMul_INC) { + address += 4; + data = ARMul_LoadWordN (state, address); + //chy 2004-05-25 + if (state->abortSig || state->Aborted) + goto L_ldc_takeabort; + + cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); + } + +//chy 2004-05-25 +L_ldc_takeabort: + if (BIT (21)) { + if (! + ((state->abortSig || state->Aborted) + && state->lateabtSig == LOW)) + LSBase = state->Base; + } + + if (state->abortSig || state->Aborted) + TAKEABORT; +} + +/* This function does the work of generating the addresses used in an + STC instruction. The code here is always post-indexed, it's up to the + caller to get the input address correct and to handle base register + modification. It also handles the Busy-Waiting. */ + +void +ARMul_STC (ARMul_State * state, ARMword instr, ARMword address) +{ + unsigned cpab; + ARMword data; + + UNDEF_LSCPCBaseWb; + + //printf("SKYEYE ARMul_STC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); + /*chy 2004-05-23 should update this function in the future,should concern dataabort */ +// skyeye_instr_debug=0;printf("SKYEYE debug end!!!!\n"); +// chy 2004-05-25 , fix it now,so needn't printf +// printf("SKYEYE ARMul_STC, should update this function!!!!!\n"); + + //exit(-1); + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->STC[CPNum]) { + /* + printf + ("SKYEYE ARMul_STC,NOT ALLOW, undefinstr, CPnum is %x, instr %x, addr %x\n", + CPNum, instr, address); + */ + ARMul_UndefInstr (state, instr); + return; + } + + /*if (ADDREXCEPT (address) || VECTORACCESS (address)) + INTERNALABORT (address);*/ + + cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data); + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) { + cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, + instr, 0); + return; + } else + cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, + &data); + } + + if (cpab == ARMul_CANT) { + /* + printf + ("SKYEYE ARMul_STC,CANT, undefinstr, CPnum is %x, instr %x, addr %x\n", + CPNum, instr, address); + */ + CPTAKEABORT; + return; + } + /*#ifndef MODE32 + if (ADDREXCEPT (address) || VECTORACCESS (address)) + INTERNALABORT (address); + #endif*/ + BUSUSEDINCPCN; +//chy 2004-05-25 + /* + if (BIT (21)) + LSBase = state->Base; + */ + cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); + ARMul_StoreWordN (state, address, data); + //chy 2004-05-25 + if (state->abortSig || state->Aborted) + goto L_stc_takeabort; + + while (cpab == ARMul_INC) { + address += 4; + cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); + ARMul_StoreWordN (state, address, data); + //chy 2004-05-25 + if (state->abortSig || state->Aborted) + goto L_stc_takeabort; + } +//chy 2004-05-25 +L_stc_takeabort: + if (BIT (21)) { + if (! + ((state->abortSig || state->Aborted) + && state->lateabtSig == LOW)) + LSBase = state->Base; + } + + if (state->abortSig || state->Aborted) + TAKEABORT; +} + +/* This function does the Busy-Waiting for an MCR instruction. */ + +void +ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) +{ + unsigned cpab; + int cm = BITS(0, 3) & 0xf; + int cp = BITS(5, 7) & 0x7; + int rd = BITS(12, 15) & 0xf; + int cn = BITS(16, 19) & 0xf; + int cpopc = BITS(21, 23) & 0x7; + + if (CPNum == 15 && source == 0) //Cache flush + { + return; + } + + //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->MCR[CPNum]) { + //chy 2004-07-19 should fix in the future ????!!!! + XDSERROR("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x", CPNum, source); + ARMul_UndefInstr (state, instr); + return; + } + + //DEBUG("SKYEYE ARMul_MCR p%d, %d, r%d, c%d, c%d, %d\n", CPNum, cpopc, rd, cn, cm, cp); + //DEBUG("plutoo: MCR not implemented\n"); + //exit(1); + //return; + + cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); + + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + + if (IntPending (state)) { + cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, + instr, 0); + return; + } else + cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, + source); + } + + if (cpab == ARMul_CANT) { + XDSERROR("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x", instr, CPNum, source); //ichfly todo + //ARMul_Abort (state, ARMul_UndefinedInstrV); + } else { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + } +} + +/* This function does the Busy-Waiting for an MCRR instruction. */ + +void +ARMul_MCRR (ARMul_State * state, ARMword instr, ARMword source1, ARMword source2) +{ + unsigned cpab; + + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->MCRR[CPNum]) { + ARMul_UndefInstr (state, instr); + return; + } + + cpab = (state->MCRR[CPNum]) (state, ARMul_FIRST, instr, source1, source2); + + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + + if (IntPending (state)) { + cpab = (state->MCRR[CPNum]) (state, ARMul_INTERRUPT, + instr, 0, 0); + return; + } else + cpab = (state->MCRR[CPNum]) (state, ARMul_BUSY, instr, + source1, source2); + } + if (cpab == ARMul_CANT) { + printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x, source %x %x\n", __FUNCTION__, CPNum, instr, source1, source2); + ARMul_Abort (state, ARMul_UndefinedInstrV); + } else { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + } +} + +/* This function does the Busy-Waiting for an MRC instruction. */ + +ARMword ARMul_MRC (ARMul_State * state, ARMword instr) +{ + int cm = BITS(0, 3) & 0xf; + int cp = BITS(5, 7) & 0x7; + int rd = BITS(12, 15) & 0xf; + int cn = BITS(16, 19) & 0xf; + int cpopc = BITS(21, 23) & 0x7; + + if (cn == 13 && cm == 0 && cp == 3) { //c13,c0,3; returns CPU svc buffer + ARMword result = state->m_currentThread->m_TSL3DS; + + if (result != -1) { + return result; + } + } + + //DEBUG("SKYEYE ARMul_MRC p%d, %d, r%d, c%d, c%d, %d\n", CPNum, cpopc, rd, cn, cm, cp); + //DEBUG("plutoo: MRC not implemented\n"); + //return; + + unsigned cpab; + ARMword result = 0; + + //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->MRC[CPNum]) { + //chy 2004-07-19 should fix in the future????!!!! + XDSERROR("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x", CPNum, instr); + ARMul_UndefInstr (state, instr); + return -1; + } + + cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) { + cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, + instr, 0); + return (0); + } else + cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, + &result); + } + if (cpab == ARMul_CANT) { + printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr); + ARMul_Abort (state, ARMul_UndefinedInstrV); + /* Parent will destroy the flags otherwise. */ + result = ECC; + } else { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + ARMul_Icycles (state, 1, 0); + } + + return result; +} + +/* This function does the Busy-Waiting for an MRRC instruction. (to verify) */ + +void +ARMul_MRRC (ARMul_State * state, ARMword instr, ARMword * dest1, ARMword * dest2) +{ + unsigned cpab; + ARMword result1 = 0; + ARMword result2 = 0; + + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->MRRC[CPNum]) { + ARMul_UndefInstr (state, instr); + return; + } + + cpab = (state->MRRC[CPNum]) (state, ARMul_FIRST, instr, &result1, &result2); + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) { + cpab = (state->MRRC[CPNum]) (state, ARMul_INTERRUPT, + instr, 0, 0); + return; + } else + cpab = (state->MRRC[CPNum]) (state, ARMul_BUSY, instr, + &result1, &result2); + } + if (cpab == ARMul_CANT) { + printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x\n", __FUNCTION__, CPNum, instr); + ARMul_Abort (state, ARMul_UndefinedInstrV); + } else { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + ARMul_Icycles (state, 1, 0); + } + + *dest1 = result1; + *dest2 = result2; +} + +/* This function does the Busy-Waiting for an CDP instruction. */ + +void +ARMul_CDP (ARMul_State * state, ARMword instr) +{ + unsigned cpab; + + //if (!CP_ACCESS_ALLOWED (state, CPNum)) { + if (!state->CDP[CPNum]) { + ARMul_UndefInstr (state, instr); + return; + } + cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr); + while (cpab == ARMul_BUSY) { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) { + cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, + instr); + return; + } else + cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr); + } + if (cpab == ARMul_CANT) + ARMul_Abort (state, ARMul_UndefinedInstrV); + else + BUSUSEDN; +} + +/* This function handles Undefined instructions, as CP isntruction. */ + +void +ARMul_UndefInstr (ARMul_State * state, ARMword instr) +{ + //std::string disasm = ARM_Disasm::Disassemble(state->pc, instr); + //ERROR("Undefined instruction!! Disasm: %s Opcode: 0x%x", disasm.c_str(), instr); + ARMul_Abort (state, ARMul_UndefinedInstrV); +} + +/* Return TRUE if an interrupt is pending, FALSE otherwise. */ + +unsigned +IntPending (ARMul_State * state) +{ + /* Any exceptions. */ + if (state->NresetSig == LOW) { + ARMul_Abort (state, ARMul_ResetV); + return TRUE; + } else if (!state->NfiqSig && !FFLAG) { + ARMul_Abort (state, ARMul_FIQV); + return TRUE; + } else if (!state->NirqSig && !IFLAG) { + ARMul_Abort (state, ARMul_IRQV); + return TRUE; + } + + return FALSE; +} + +/* Align a word access to a non word boundary. */ + +ARMword +ARMul_Align (ARMul_State* state, ARMword address, ARMword data) +{ + /* This code assumes the address is really unaligned, + as a shift by 32 is undefined in C. */ + + address = (address & 3) << 3; /* Get the word address. */ + return ((data >> address) | (data << (32 - address))); /* rot right */ +} + +/* This routine is used to call another routine after a certain number of + cycles have been executed. The first parameter is the number of cycles + delay before the function is called, the second argument is a pointer + to the function. A delay of zero doesn't work, just call the function. */ + +void +ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay, + unsigned (*what) (ARMul_State *)) +{ + unsigned int when; + struct EventNode *event; + + if (state->EventSet++ == 0) + state->Now = ARMul_Time (state); + when = (state->Now + delay) % EVENTLISTSIZE; + event = (struct EventNode *) malloc (sizeof (struct EventNode)); + if (!event) { + printf ("SKYEYE:ARMul_ScheduleEvent: malloc event error\n"); + exit(-1); + //skyeye_exit (-1); + } + event->func = what; + event->next = *(state->EventPtr + when); + *(state->EventPtr + when) = event; +} + +/* This routine is called at the beginning of + every cycle, to envoke scheduled events. */ + +void +ARMul_EnvokeEvent (ARMul_State * state) +{ + static unsigned int then; + + then = state->Now; + state->Now = ARMul_Time (state) % EVENTLISTSIZE; + if (then < state->Now) + /* Schedule events. */ + EnvokeList (state, then, state->Now); + else if (then > state->Now) { + /* Need to wrap around the list. */ + EnvokeList (state, then, EVENTLISTSIZE - 1L); + EnvokeList (state, 0L, state->Now); + } +} + +/* Envokes all the entries in a range. */ + +static void +EnvokeList (ARMul_State * state, unsigned int from, unsigned int to) +{ + for (; from <= to; from++) { + struct EventNode *anevent; + + anevent = *(state->EventPtr + from); + while (anevent) { + (anevent->func) (state); + state->EventSet--; + anevent = anevent->next; + } + *(state->EventPtr + from) = NULL; + } +} + +/* This routine is returns the number of clock ticks since the last reset. */ + +unsigned int +ARMul_Time (ARMul_State * state) +{ + return (state->NumScycles + state->NumNcycles + + state->NumIcycles + state->NumCcycles + state->NumFcycles); +} diff --git a/source/arm/interpreter/armvirt.cpp b/source/arm/interpreter/armvirt.cpp new file mode 100644 index 0000000..200603a --- /dev/null +++ b/source/arm/interpreter/armvirt.cpp @@ -0,0 +1,235 @@ +/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file contains a complete ARMulator memory model, modelling a +"virtual memory" system. A much simpler model can be found in armfast.c, +and that model goes faster too, but has a fixed amount of memory. This +model's memory has 64K pages, allocated on demand from a 64K entry page +table. The routines PutWord and GetWord implement this. Pages are never +freed as they might be needed again. A single area of memory may be +defined to generate aborts. */ + +#include "Common.h" +#include "Kernel.h" +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" + +#include "arm/memory.h" + + +#define dumpstack 1 +#define dumpstacksize 0x10 +#define maxdmupaddr 0x0033a850 + +/*ARMword ARMul_GetCPSR (ARMul_State * state) { +return 0; +} +ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode) { +return 0; +} +void ARMul_SetCPSR (ARMul_State * state, ARMword value) { + +} +void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) { + +}*/ + +void ARMul_Icycles(ARMul_State * state, unsigned number, ARMword address) { +} + +void ARMul_Ccycles(ARMul_State * state, unsigned number, ARMword address) { +} + +ARMword ARMul_LoadInstrS(ARMul_State * state, ARMword address, ARMword isize) { + state->NumScycles++; + +#ifdef HOURGLASS + if ((state->NumScycles & HOURGLASS_RATE) == 0) { + HOURGLASS; + } +#endif + if (isize == 2) + { + u16 data; + if (unlikely(state->m_MemoryMap->Read16(address, data) != Success)) + { + XDSERROR("size 2 error reading from %08x", address); + } + return data; + } + else + { + u32 data; + if (unlikely(state->m_MemoryMap->Read32(address, data) != Success)) + { + XDSERROR("size 4 error reading from %08x", address); + } + return data; + } +} + +ARMword ARMul_LoadInstrN(ARMul_State * state, ARMword address, ARMword isize) { + state->NumNcycles++; + + if (isize == 2) + { + u16 data; + if (unlikely(state->m_MemoryMap->Read16(address, data) != Success)) + { + XDSERROR("size 2 error reading from %08x", address); + } + return data; + } + else + { + u32 data; + if (unlikely(state->m_MemoryMap->Read32(address, data) != Success)) + { + XDSERROR("size 4 error reading from %08x", address); + } + return data; + } +} + +ARMword ARMul_ReLoadInstr(ARMul_State * state, ARMword address, ARMword isize) { + ARMword data; + + if ((isize == 2) && (address & 0x2)) { + u16 data; + if (unlikely(state->m_MemoryMap->Read16(address, data) != Success)) + { + XDSERROR("error reading from %08x", address); + } + return data & 0xFFFF; + } + if (unlikely(state->m_MemoryMap->Read32(address, data) != Success)) + { + XDSERROR("size 4 error reading from %08x", address); + } + return data; +} + +ARMword ARMul_ReadWord(ARMul_State * state, ARMword address) { + u32 data; + if (unlikely(state->m_MemoryMap->Read32(address, data) != Success)) + { + XDSERROR("error %s thread %u reading from %08x", state->m_currentThread->m_owner->GetName(), state->m_currentThread->m_thread_id, address); + } + return data; +} + +ARMword ARMul_LoadWordS(ARMul_State * state, ARMword address) { + state->NumScycles++; + return ARMul_ReadWord(state, address); +} + +ARMword ARMul_LoadWordN(ARMul_State * state, ARMword address) { + state->NumNcycles++; + return ARMul_ReadWord(state, address); +} + +ARMword ARMul_LoadHalfWord(ARMul_State * state, ARMword address) { + state->NumNcycles++; + u16 data; + if (unlikely(state->m_MemoryMap->Read16(address, data) != Success)) + { + XDSERROR("error %s thread %u error reading from hword from %08x", state->m_currentThread->m_owner->GetName(), state->m_currentThread->m_thread_id, address); + } + return data; +} + +ARMword ARMul_ReadByte(ARMul_State * state, ARMword address) { + u8 data; + if (unlikely(state->m_MemoryMap->Read8(address, data) != Success)) + { + XDSERROR("error %s thread %u reading byte from %08x", state->m_currentThread->m_owner->GetName(), state->m_currentThread->m_thread_id, address); + data = 0x10; + } + return data; +} + +ARMword ARMul_LoadByte(ARMul_State * state, ARMword address) { + state->NumNcycles++; + return ARMul_ReadByte(state, address); +} + +void ARMul_StoreHalfWord(ARMul_State * state, ARMword address, ARMword data) { + state->NumNcycles++; + if (unlikely(state->m_MemoryMap->Write16(address, data) != Success)) + { + XDSERROR("error %s thread %u writing %04x to %08x", state->m_currentThread->m_owner->GetName(), state->m_currentThread->m_thread_id, data, address); + } +} + +void ARMul_StoreByte(ARMul_State * state, ARMword address, ARMword data) { + state->NumNcycles++; + ARMul_WriteByte(state, address, data); +} + +ARMword ARMul_SwapWord(ARMul_State * state, ARMword address, ARMword data) { + ARMword temp; + state->NumNcycles++; + temp = ARMul_ReadWord(state, address); + state->NumNcycles++; + if (unlikely(state->m_MemoryMap->Write32(address, data) != Success)) + { + XDSERROR("error writing to %08x", address); + } + return temp; +} + +ARMword ARMul_SwapByte(ARMul_State * state, ARMword address, ARMword data) { + ARMword temp; + temp = ARMul_LoadByte(state, address); + if (unlikely(state->m_MemoryMap->Write8(address, data) != Success)) + { + XDSERROR("error writing to %08x", address); + } + return temp; +} + +void ARMul_WriteWord(ARMul_State * state, ARMword address, ARMword data) { + if (unlikely(state->m_MemoryMap->Write32(address, data) != Success)) + { + XDSERROR("error writing to %08x data %08x", address,data); + } +} + +void ARMul_WriteByte(ARMul_State * state, ARMword address, ARMword data) +{ + if (unlikely(state->m_MemoryMap->Write8(address, data) != Success)) + { + XDSERROR("error %s thread %u writing %02x to %08x", state->m_currentThread->m_owner->GetName(), state->m_currentThread->m_thread_id, data, address); + } +} +void ARMul_WriteDouble(ARMul_State* state, ARMword address, u64 data) { + ARMul_WriteWord(state, address, (u32)(data >> 0)); + ARMul_WriteWord(state, address + 4, (u32)(data >> 32)); +} + + +void ARMul_StoreWordS(ARMul_State * state, ARMword address, ARMword data) +{ + state->NumScycles++; + ARMul_WriteWord(state, address, data); +} + +void ARMul_StoreWordN(ARMul_State * state, ARMword address, ARMword data) +{ + state->NumNcycles++; + ARMul_WriteWord(state, address, data); +} diff --git a/source/arm/interpreter/thumbemu.cpp b/source/arm/interpreter/thumbemu.cpp new file mode 100644 index 0000000..4849437 --- /dev/null +++ b/source/arm/interpreter/thumbemu.cpp @@ -0,0 +1,579 @@ +/* thumbemu.c -- Thumb instruction emulation. + Copyright (C) 1996, Cygnus Software Technologies Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We can provide simple Thumb simulation by decoding the Thumb +instruction into its corresponding ARM instruction, and using the +existing ARM simulator. */ + +#include "Kernel.h" + +#include "arm/skyeye_common/skyeye_defs.h" + +#ifndef MODET /* required for the Thumb instruction support */ +#if 1 +#error "MODET needs to be defined for the Thumb world to work" +#else +#define MODET (1) +#endif +#endif + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/armemu.h" +#include "arm/skyeye_common/armos.h" + + +/* Decode a 16bit Thumb instruction. The instruction is in the low + 16-bits of the tinstr field, with the following Thumb instruction + held in the high 16-bits. Passing in two Thumb instructions allows + easier simulation of the special dual BL instruction. */ + +tdstate +ARMul_ThumbDecode( +ARMul_State *state, +ARMword pc, +ARMword tinstr, +ARMword *ainstr) +{ + tdstate valid = t_decoded; /* default assumes a valid instruction */ + ARMword next_instr; + + if (state->bigendSig) { + next_instr = tinstr & 0xFFFF; + tinstr >>= 16; + } + else { + next_instr = tinstr >> 16; + tinstr &= 0xFFFF; + } + +#if 1 /* debugging to catch non updates */ + * ainstr = 0xDEADC0DE; +#endif + + switch ((tinstr & 0xF800) >> 11) { + case 0: /* LSL */ + case 1: /* LSR */ + case 2: /* ASR */ + /* Format 1 */ + *ainstr = 0xE1B00000 /* base opcode */ + | ((tinstr & 0x1800) >> (11 - 5)) /* shift type */ + | ((tinstr & 0x07C0) << (7 - 6)) /* imm5 */ + | ((tinstr & 0x0038) >> 3) /* Rs */ + | ((tinstr & 0x0007) << 12); /* Rd */ + break; + case 3: /* ADD/SUB */ + /* Format 2 */ + { + ARMword subset[4] = { + 0xE0900000, /* ADDS Rd,Rs,Rn */ + 0xE0500000, /* SUBS Rd,Rs,Rn */ + 0xE2900000, /* ADDS Rd,Rs,#imm3 */ + 0xE2500000 /* SUBS Rd,Rs,#imm3 */ + }; + /* It is quicker indexing into a table, than performing switch + or conditionals: */ + *ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */ + | ((tinstr & 0x01C0) >> 6) /* Rn or imm3 */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rs */ + | ((tinstr & 0x0007) << (12 - 0)); /* Rd */ + } + break; + case 4: /* MOV */ + case 5: /* CMP */ + case 6: /* ADD */ + case 7: /* SUB */ + /* Format 3 */ + { + ARMword subset[4] = { + 0xE3B00000, /* MOVS Rd,#imm8 */ + 0xE3500000, /* CMP Rd,#imm8 */ + 0xE2900000, /* ADDS Rd,Rd,#imm8 */ + 0xE2500000, /* SUBS Rd,Rd,#imm8 */ + }; + *ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */ + | ((tinstr & 0x00FF) >> 0) /* imm8 */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rn */ + | ((tinstr & 0x0700) << (12 - 8)); /* Rd */ + } + break; + case 8: /* Arithmetic and high register transfers */ + /* TODO: Since the subsets for both Format 4 and Format 5 + instructions are made up of different ARM encodings, we could + save the following conditional, and just have one large + subset. */ + if ((tinstr & (1 << 10)) == 0) { + /* Format 4 */ + enum OpcodeType { t_norm, t_shift, t_neg, t_mul }; + struct ThumbOpcode { + ARMword opcode; + OpcodeType otype; + }; + + ThumbOpcode subset[16] = { + { + 0xE0100000, t_norm + }, /* ANDS Rd,Rd,Rs */ + { + 0xE0300000, t_norm + }, /* EORS Rd,Rd,Rs */ + { + 0xE1B00010, t_shift + }, /* MOVS Rd,Rd,LSL Rs */ + { + 0xE1B00030, t_shift + }, /* MOVS Rd,Rd,LSR Rs */ + { + 0xE1B00050, t_shift + }, /* MOVS Rd,Rd,ASR Rs */ + { + 0xE0B00000, t_norm + }, /* ADCS Rd,Rd,Rs */ + { + 0xE0D00000, t_norm + }, /* SBCS Rd,Rd,Rs */ + { + 0xE1B00070, t_shift + }, /* MOVS Rd,Rd,ROR Rs */ + { + 0xE1100000, t_norm + }, /* TST Rd,Rs */ + { + 0xE2700000, t_neg + }, /* RSBS Rd,Rs,#0 */ + { + 0xE1500000, t_norm + }, /* CMP Rd,Rs */ + { + 0xE1700000, t_norm + }, /* CMN Rd,Rs */ + { + 0xE1900000, t_norm + }, /* ORRS Rd,Rd,Rs */ + { + 0xE0100090, t_mul + }, /* MULS Rd,Rd,Rs */ + { + 0xE1D00000, t_norm + }, /* BICS Rd,Rd,Rs */ + { + 0xE1F00000, t_norm + } /* MVNS Rd,Rs */ + }; + *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ + switch (subset[(tinstr & 0x03C0) >> 6].otype) { + case t_norm: + *ainstr |= ((tinstr & 0x0007) << 16) /* Rn */ + | ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0038) >> 3); /* Rs */ + break; + case t_shift: + *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0007) >> 0) /* Rm */ + | ((tinstr & 0x0038) << (8 - 3)); /* Rs */ + break; + case t_neg: + *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)); /* Rn */ + break; + case t_mul: + *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */ + | ((tinstr & 0x0007) << 8) /* Rs */ + | ((tinstr & 0x0038) >> 3); /* Rm */ + break; + } + } + else { + /* Format 5 */ + ARMword Rd = ((tinstr & 0x0007) >> 0); + ARMword Rs = ((tinstr & 0x0038) >> 3); + if (tinstr & (1 << 7)) + Rd += 8; + if (tinstr & (1 << 6)) + Rs += 8; + switch ((tinstr & 0x03C0) >> 6) { + case 0x0: /* ADD Rd,Rd,Hs */ + case 0x1: /* ADD Rd,Rd,Hs */ + case 0x2: /* ADD Hd,Hd,Rs */ + case 0x3: /* ADD Hd,Hd,Hs */ + *ainstr = 0xE0800000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0x4: /* CMP Rd,Hs */ + case 0x5: /* CMP Rd,Hs */ + case 0x6: /* CMP Hd,Rs */ + case 0x7: /* CMP Hd,Hs */ + *ainstr = 0xE1500000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0x8: /* MOV Rd,Hs */ + case 0x9: /* MOV Rd,Hs */ + case 0xA: /* MOV Hd,Rs */ + case 0xB: /* MOV Hd,Hs */ + *ainstr = 0xE1A00000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0xC: /* BX Rs */ + case 0xD: /* BX Hs */ + *ainstr = 0xE12FFF10 /* base */ + | ((tinstr & 0x0078) >> 3); /* Rd */ + break; + case 0xE: /* BLX */ + case 0xF: /* BLX */ + if (state->is_v5) { + *ainstr = 0xE1200030 /* base */ + | (Rs << 0); /* Rm */ + } + else { + valid = t_undefined; + } + break; + } + } + break; + case 9: /* LDR Rd,[PC,#imm8] */ + /* Format 6 */ + *ainstr = 0xE59F0000 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | ((tinstr & 0x00FF) << (2 - 0)); /* off8 */ + break; + case 10: + case 11: + /* TODO: Format 7 and Format 8 perform the same ARM encoding, so + the following could be merged into a single subset, saving on + the following boolean: */ + if ((tinstr & (1 << 9)) == 0) { + /* Format 7 */ + ARMword subset[4] = { + 0xE7800000, /* STR Rd,[Rb,Ro] */ + 0xE7C00000, /* STRB Rd,[Rb,Ro] */ + 0xE7900000, /* LDR Rd,[Rb,Ro] */ + 0xE7D00000 /* LDRB Rd,[Rb,Ro] */ + }; + *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> 6); /* Ro */ + } + else { + /* Format 8 */ + ARMword subset[4] = { + 0xE18000B0, /* STRH Rd,[Rb,Ro] */ + 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */ + 0xE19000B0, /* LDRH Rd,[Rb,Ro] */ + 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */ + }; + *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> 6); /* Ro */ + } + break; + case 12: /* STR Rd,[Rb,#imm5] */ + case 13: /* LDR Rd,[Rb,#imm5] */ + case 14: /* STRB Rd,[Rb,#imm5] */ + case 15: /* LDRB Rd,[Rb,#imm5] */ + /* Format 9 */ + { + ARMword subset[4] = { + 0xE5800000, /* STR Rd,[Rb,#imm5] */ + 0xE5900000, /* LDR Rd,[Rb,#imm5] */ + 0xE5C00000, /* STRB Rd,[Rb,#imm5] */ + 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */ + }; + /* The offset range defends on whether we are transferring a + byte or word value: */ + *ainstr = subset[(tinstr & 0x1800) >> 11] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */ + } + break; + case 16: /* STRH Rd,[Rb,#imm5] */ + case 17: /* LDRH Rd,[Rb,#imm5] */ + /* Format 10 */ + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE1D000B0 /* LDRH */ + : 0xE1C000B0) /* STRH */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */ + | ((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */ + break; + case 18: /* STR Rd,[SP,#imm8] */ + case 19: /* LDR Rd,[SP,#imm8] */ + /* Format 11 */ + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE59D0000 /* LDR */ + : 0xE58D0000) /* STR */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | ((tinstr & 0x00FF) << 2); /* off8 */ + break; + case 20: /* ADD Rd,PC,#imm8 */ + case 21: /* ADD Rd,SP,#imm8 */ + /* Format 12 */ + if ((tinstr & (1 << 11)) == 0) { + /* NOTE: The PC value used here should by word aligned */ + /* We encode shift-left-by-2 in the rotate immediate field, + so no shift of off8 is needed. */ + *ainstr = 0xE28F0F00 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | (tinstr & 0x00FF); /* off8 */ + } + else { + /* We encode shift-left-by-2 in the rotate immediate field, + so no shift of off8 is needed. */ + *ainstr = 0xE28D0F00 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | (tinstr & 0x00FF); /* off8 */ + } + break; + case 22: + case 23: + if ((tinstr & 0x0F00) == 0x0000) { + // NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30): + *ainstr = ((tinstr & (1 << 7)) // base + ? 0xE24DDF00 // SUB + : 0xE28DDF00) // ADD + | (tinstr & 0x007F); // off7 + } + else if ((tinstr & 0x0F00) == 0x0e00) + *ainstr = 0xEF000000 | SWI_Breakpoint; + else { + if ((tinstr & 0x600) == 0x400) + { + /* Format 14 */ + u32 subset[4] = { + 0xE92D0000, /* STMDB sp!,{rlist} */ + 0xE92D4000, /* STMDB sp!,{rlist,lr} */ + 0xE8BD0000, /* LDMIA sp!,{rlist} */ + 0xE8BD8000 /* LDMIA sp!,{rlist,pc} */ + }; + *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */ + | (tinstr & 0x00FF); /* mask8 */ + } + else + { + //e6bf1071 sxth r1, r1 + //e6af1071 sxtb r1, r1 + //e6ff1078 uxth r1, r8 + //e6ef1078 uxtb r1, r8 + + u32 subset[4] = { //Bit 12 - 15 dest Bit 0 - 3 src + 0xe6ff0070, /* uxth */ + 0xe6ef0070, /* uxtb */ + 0xe6bf0070, /* sxth */ + 0xe6af0070 /* sxtb */ + }; + + if ((tinstr & 0xF00) == 0x200) //Bit(7) unsigned (set = sxt. cleared = uxt) Bit(6) byte (set = .xtb cleared = .xth) Bit 5-3 Rb src Bit 2-0 Rd dest + { + *ainstr = subset[((tinstr & (0x3 << 6)) >> 6)] | + (tinstr & 0x7) << 12 | + (tinstr & 0x38) >> 3; + } + else if ((tinstr & 0x0FC0) == 0x0A00){ + u32 Destr = (tinstr & 0x7); + u32 srcr = ((tinstr >> 3) & 0x7); + *ainstr = 0xE6BF0F30 | srcr | (Destr << 12); + + } + else + { + valid = t_undefined; + XDSERROR("unk thumb instr %04x", tinstr); + } + + } + } + break; + case 24: /* STMIA */ + case 25: /* LDMIA */ + /* Format 15 */ + { + u32 Rb = (tinstr & 0x0700) >> 8; + if ((1 << Rb)&tinstr) //no write back if the register is in the list + { + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE8900000 /* LDMIA */ + : 0xE8800000) /* STMIA */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rb */ + | (tinstr & 0x00FF); /* mask8 */ + break; + } + else + { + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE8B00000 /* LDMIA */ + : 0xE8A00000) /* STMIA */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rb */ + | (tinstr & 0x00FF); /* mask8 */ + break; + } + } + case 26: /* Bcc */ + case 27: /* Bcc/SWI */ + if ((tinstr & 0x0F00) == 0x0F00) { + if (tinstr == (ARMul_ABORTWORD & 0xffff) && + state->AbortAddr == pc) { + *ainstr = ARMul_ABORTWORD; + break; + } + /* Format 17 : SWI */ + *ainstr = 0xEF000000; + /* Breakpoint must be handled specially. */ + if ((tinstr & 0x00FF) == 0x18) + *ainstr |= ((tinstr & 0x00FF) << 16); + /* New breakpoint value. See gdb/arm-tdep.c */ + else if ((tinstr & 0x00FF) == 0xFE) + *ainstr |= SWI_Breakpoint; + else + *ainstr |= (tinstr & 0x00FF); + } + else if ((tinstr & 0x0F00) != 0x0E00) { + /* Format 16 */ + int doit = FALSE; + /* TODO: Since we are doing a switch here, we could just add + the SWI and undefined instruction checks into this + switch to same on a couple of conditionals: */ + switch ((tinstr & 0x0F00) >> 8) { + case EQ: + doit = ZFLAG; + break; + case NE: + doit = !ZFLAG; + break; + case VS: + doit = VFLAG; + break; + case VC: + doit = !VFLAG; + break; + case MI: + doit = NFLAG; + break; + case PL: + doit = !NFLAG; + break; + case CS: + doit = CFLAG; + break; + case CC: + doit = !CFLAG; + break; + case HI: + doit = (CFLAG && !ZFLAG); + break; + case LS: + doit = (!CFLAG || ZFLAG); + break; + case GE: + doit = ((!NFLAG && !VFLAG) + || (NFLAG && VFLAG)); + break; + case LT: + doit = ((NFLAG && !VFLAG) + || (!NFLAG && VFLAG)); + break; + case GT: + doit = ((!NFLAG && !VFLAG && !ZFLAG) + || (NFLAG && VFLAG && !ZFLAG)); + break; + case LE: + doit = ((NFLAG && !VFLAG) + || (!NFLAG && VFLAG)) || ZFLAG; + break; + } + if (doit) { + state->Reg[15] = (pc + 4 + + (((tinstr & 0x7F) << 1) + | ((tinstr & (1 << 7)) ? + 0xFFFFFF00 : 0))); + FLUSHPIPE; + } + valid = t_branch; + } + else /* UNDEFINED : cc=1110(AL) uses different format */ + valid = t_undefined; + break; + case 28: /* B */ + /* Format 18 */ + state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1) + | ((tinstr & (1 << 10)) ? + 0xFFFFF800 : 0))); + FLUSHPIPE; + valid = t_branch; + break; + case 29: + if (tinstr & 0x1) + valid = t_undefined; + else{ + /* BLX 1 for armv5t and above */ + ARMword tmp = (pc + 2); + state->Reg[15] = + (state->Reg[14] + ((tinstr & 0x07FF) << 1)) & 0xFFFFFFFC; + state->Reg[14] = (tmp | 1); + CLEART; + LOG("After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x", state->Reg[14], state->Reg[15], (tinstr & 0x7FF) << 1); + valid = t_branch; + FLUSHPIPE; + } + break; + case 30: /* BL instruction 1 */ + /* Format 19 */ + /* There is no single ARM instruction equivalent for this Thumb + instruction. To keep the simulation simple (from the user + perspective) we check if the following instruction is the + second half of this BL, and if it is we simulate it + immediately. */ + state->Reg[14] = state->Reg[15] + + (((tinstr & 0x07FF) << 12) + | ((tinstr & (1 << 10)) ? 0xFF800000 : 0)); + valid = t_branch; /* in-case we don't have the 2nd half */ + //tinstr = next_instr; /* move the instruction down */ + //if (((tinstr & 0xF800) >> 11) != 31) + // break; /* exit, since not correct instruction */ + /* else we fall through to process the second half of the BL */ + //pc += 2; /* point the pc at the 2nd half */ + state->Reg[15] = pc + 2; + FLUSHPIPE; + break; + case 31: /* BL instruction 2 */ + /* Format 19 */ + /* There is no single ARM instruction equivalent for this + instruction. Also, it should only ever be matched with the + fmt19 "BL instruction 1" instruction. However, we do allow + the simulation of it on its own, with undefined results if + r14 is not suitably initialised. */ + { + ARMword tmp = (pc + 2); + state->Reg[15] = + (state->Reg[14] + ((tinstr & 0x07FF) << 1)); + state->Reg[14] = (tmp | 1); + valid = t_branch; + FLUSHPIPE; + } + break; + } + + return valid; +} diff --git a/source/arm/memory.h b/source/arm/memory.h new file mode 100644 index 0000000..f6d8a13 --- /dev/null +++ b/source/arm/memory.h @@ -0,0 +1,28 @@ +class Memory { +public: + static void Write8(u32 addr, u8 val) { + + } + static void Write16(u32 addr, u16 val) { + + } + static void Write32(u32 addr, u32 val) { + + } + static u8 Read8(u32 addr) { + return 0; + } + static u16 Read16(u32 addr) { + return 0; + } + static u32 Read32(u32 addr) { + return 0; + } +}; + +class HLE { +public: + static void CallSVC(u32 i) { + + } +}; diff --git a/source/arm/skyeye_common/arm_regformat.h b/source/arm/skyeye_common/arm_regformat.h new file mode 100644 index 0000000..ee0e86e --- /dev/null +++ b/source/arm/skyeye_common/arm_regformat.h @@ -0,0 +1,188 @@ +#ifndef __ARM_REGFORMAT_H__ +#define __ARM_REGFORMAT_H__ + +enum { + R0 = 0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + R13, + LR, + R15, //PC, + CPSR_REG, + SPSR_REG, + + PHYS_PC, + R13_USR, + R14_USR, + R13_SVC, + R14_SVC, + R13_ABORT, + R14_ABORT, + R13_UNDEF, + R14_UNDEF, + R13_IRQ, + R14_IRQ, + R8_FIRQ, + R9_FIRQ, + R10_FIRQ, + R11_FIRQ, + R12_FIRQ, + R13_FIRQ, + R14_FIRQ, + SPSR_INVALID1, + SPSR_INVALID2, + SPSR_SVC, + SPSR_ABORT, + SPSR_UNDEF, + SPSR_IRQ, + SPSR_FIRQ, + MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */ + BANK_REG, + EXCLUSIVE_TAG, + EXCLUSIVE_STATE, + EXCLUSIVE_RESULT, + + // c0 - Information registers + CP15_BASE, + CP15_C0 = CP15_BASE, + CP15_C0_C0 = CP15_C0, + CP15_MAIN_ID = CP15_C0_C0, + CP15_CACHE_TYPE, + CP15_TCM_STATUS, + CP15_TLB_TYPE, + CP15_CPU_ID, + CP15_C0_C1, + CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1, + CP15_PROCESSOR_FEATURE_1, + CP15_DEBUG_FEATURE_0, + CP15_AUXILIARY_FEATURE_0, + CP15_MEMORY_MODEL_FEATURE_0, + CP15_MEMORY_MODEL_FEATURE_1, + CP15_MEMORY_MODEL_FEATURE_2, + CP15_MEMORY_MODEL_FEATURE_3, + CP15_C0_C2, + CP15_ISA_FEATURE_0 = CP15_C0_C2, + CP15_ISA_FEATURE_1, + CP15_ISA_FEATURE_2, + CP15_ISA_FEATURE_3, + CP15_ISA_FEATURE_4, + + // c1 - Control registers + CP15_C1_C0, + CP15_CONTROL = CP15_C1_C0, + CP15_AUXILIARY_CONTROL, + CP15_COPROCESSOR_ACCESS_CONTROL, + + // c2 - Translation table registers + CP15_C2, + CP15_C2_C0 = CP15_C2, + CP15_TRANSLATION_BASE = CP15_C2_C0, + CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE, + CP15_TRANSLATION_BASE_TABLE_1, + CP15_TRANSLATION_BASE_CONTROL, + CP15_DOMAIN_ACCESS_CONTROL, + CP15_RESERVED, + + // c5 - Fault status registers + CP15_FAULT_STATUS, + CP15_INSTR_FAULT_STATUS, + CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS, + CP15_INST_FSR, + + // c6 - Fault Address registers + CP15_FAULT_ADDRESS, + CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS, + CP15_WFAR, + CP15_IFAR, + + // c7 - Cache operation registers + CP15_WAIT_FOR_INTERRUPT, + CP15_PHYS_ADDRESS, + CP15_INVALIDATE_INSTR_CACHE, + CP15_INVALIDATE_INSTR_CACHE_USING_MVA, + CP15_INVALIDATE_INSTR_CACHE_USING_INDEX, + CP15_FLUSH_PREFETCH_BUFFER, + CP15_FLUSH_BRANCH_TARGET_CACHE, + CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY, + CP15_INVALIDATE_DATA_CACHE, + CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA, + CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, + CP15_INVALIDATE_DATA_AND_INSTR_CACHE, + CP15_CLEAN_DATA_CACHE, + CP15_CLEAN_DATA_CACHE_LINE_USING_MVA, + CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX, + CP15_DATA_SYNC_BARRIER, + CP15_DATA_MEMORY_BARRIER, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, + + // c8 - TLB operations + CP15_INVALIDATE_ITLB, + CP15_INVALIDATE_ITLB_SINGLE_ENTRY, + CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_ITLB_ENTRY_ON_MVA, + CP15_INVALIDATE_DTLB, + CP15_INVALIDATE_DTLB_SINGLE_ENTRY, + CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_DTLB_ENTRY_ON_MVA, + CP15_INVALIDATE_UTLB, + CP15_INVALIDATE_UTLB_SINGLE_ENTRY, + CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_UTLB_ENTRY_ON_MVA, + + // c9 - Data cache lockdown register + CP15_DATA_CACHE_LOCKDOWN, + + // c10 - TLB/Memory map registers + CP15_TLB_LOCKDOWN, + CP15_PRIMARY_REGION_REMAP, + CP15_NORMAL_REGION_REMAP, + + // c13 - Thread related registers + CP15_PID, + CP15_CONTEXT_ID, + CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write + CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W) + CP15_THREAD_PRW, // Thread ID register - Privileged R/W only. + + // c15 - Performance and TLB lockdown registers + CP15_PERFORMANCE_MONITOR_CONTROL, + CP15_CYCLE_COUNTER, + CP15_COUNT_0, + CP15_COUNT_1, + CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY, + CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY, + CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS, + CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS, + CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE, + CP15_TLB_DEBUG_CONTROL, + + // Skyeye defined + CP15_TLB_FAULT_ADDR, + CP15_TLB_FAULT_STATUS, + + // VFP registers + VFP_BASE, + VFP_FPSID = VFP_BASE, + VFP_FPSCR, + VFP_FPEXC, + + MAX_REG_NUM, +}; + +#define CP15(idx) (idx - CP15_BASE) +#define VFP_OFFSET(x) (x - VFP_BASE) + + +#endif diff --git a/source/arm/skyeye_common/armcpu.h b/source/arm/skyeye_common/armcpu.h new file mode 100644 index 0000000..6548812 --- /dev/null +++ b/source/arm/skyeye_common/armcpu.h @@ -0,0 +1,78 @@ +/* + * arm + * armcpu.h + * + * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ARM_CPU_H__ +#define __ARM_CPU_H__ + +#include +#include + +#include "arm/skyeye_common/armdefs.h" + +typedef struct ARM_CPU_State_s { + ARMul_State * core; + uint32_t core_num; + /* The core id that boot from + */ + uint32_t boot_core_id; +}ARM_CPU_State; + +//static ARM_CPU_State* get_current_cpu(){ +// machine_config_t* mach = get_current_mach(); +// /* Casting a conf_obj_t to ARM_CPU_State type */ +// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj; +// +// return cpu; +//} + +/** +* @brief Get the core instance boot from +* +* @return +*/ +//static ARMul_State* get_boot_core(){ +// ARM_CPU_State* cpu = get_current_cpu(); +// return &cpu->core[cpu->boot_core_id]; +//} +/** +* @brief Get the instance of running core +* +* @return the core instance +*/ +//static ARMul_State* get_current_core(){ +// /* Casting a conf_obj_t to ARM_CPU_State type */ +// int id = Common::CurrentThreadId(); +// /* If thread is not in running mode, we should give the boot core */ +// if(get_thread_state(id) != Running_state){ +// return get_boot_core(); +// } +// /* Judge if we are running in paralell or sequenial */ +// if(thread_exist(id)){ +// conf_object_t* conf_obj = get_current_exec_priv(id); +// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t"); +// } +// +// return NULL; +//} + +#define CURRENT_CORE get_current_core() + +#endif + diff --git a/source/arm/skyeye_common/armdefs.h b/source/arm/skyeye_common/armdefs.h new file mode 100644 index 0000000..3706c92 --- /dev/null +++ b/source/arm/skyeye_common/armdefs.h @@ -0,0 +1,835 @@ +/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ARMDEFS_H_ +#define _ARMDEFS_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_regformat.h" +#include "Common.h" +#include "arm/skyeye_common/armmmu.h" +#include "arm/skyeye_common/skyeye_defs.h" + +#if EMU_PLATFORM == PLATFORM_LINUX +#include +#include +#endif + +#if 0 +#if 0 +#define DIFF_STATE 1 +#define __FOLLOW_MODE__ 0 +#else +#define DIFF_STATE 0 +#define __FOLLOW_MODE__ 1 +#endif +#endif + +#ifndef FALSE +#define FALSE 0 +#define TRUE 1 +#endif + +#define LOW 0 +#define HIGH 1 +#define LOWHIGH 1 +#define HIGHLOW 2 + +//#define DBCT_TEST_SPEED +#define DBCT_TEST_SPEED_SEC 10 + +#define ARM_BYTE_TYPE 0 +#define ARM_HALFWORD_TYPE 1 +#define ARM_WORD_TYPE 2 + +//the define of cachetype +#define NONCACHE 0 +#define DATACACHE 1 +#define INSTCACHE 2 + +#define POS(i) ( (~(i)) >> 31 ) +#define NEG(i) ( (i) >> 31 ) + +#ifndef __STDC__ +typedef char *VoidStar; +#endif + +typedef u64 ARMdword; // must be 64 bits wide +typedef u32 ARMword; // must be 32 bits wide +typedef u16 ARMhword; // must be 16 bits wide +typedef u8 ARMbyte; // must be 8 bits wide +typedef struct ARMul_State ARMul_State; +typedef struct ARMul_io ARMul_io; +typedef struct ARMul_Energy ARMul_Energy; + + +typedef unsigned ARMul_CPInits(ARMul_State* state); +typedef unsigned ARMul_CPExits(ARMul_State* state); +typedef unsigned ARMul_LDCs(ARMul_State* state, unsigned type, ARMword instr, ARMword value); +typedef unsigned ARMul_STCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value); +typedef unsigned ARMul_MRCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value); +typedef unsigned ARMul_MCRs(ARMul_State* state, unsigned type, ARMword instr, ARMword value); +typedef unsigned ARMul_MRRCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value1, ARMword* value2); +typedef unsigned ARMul_MCRRs(ARMul_State* state, unsigned type, ARMword instr, ARMword value1, ARMword value2); +typedef unsigned ARMul_CDPs(ARMul_State* state, unsigned type, ARMword instr); +typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value); +typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value); + + +//added by ksh,2004-3-5 +struct ARMul_io +{ + ARMword *instr; // to display the current interrupt state + ARMword *net_flag; // to judge if network is enabled + ARMword *net_int; // netcard interrupt + + //ywc,2004-04-01 + ARMword *ts_int; + ARMword *ts_is_enable; + ARMword *ts_addr_begin; + ARMword *ts_addr_end; + ARMword *ts_buffer; +}; + +/* added by ksh,2004-11-26,some energy profiling */ +struct ARMul_Energy +{ + int energy_prof; /* BUG200103282109 : for energy profiling */ + int enable_func_energy; /* BUG200105181702 */ + char *func_energy; + int func_display; /* BUG200103311509 : for function call display */ + int func_disp_start; /* BUG200104191428 : to start func profiling */ + char *start_func; /* BUG200104191428 */ + + FILE *outfile; /* BUG200105201531 : direct console to file */ + long long tcycle, pcycle; + float t_energy; + void *cur_task; /* BUG200103291737 */ + long long t_mem_cycle, t_idle_cycle, t_uart_cycle; + long long p_mem_cycle, p_idle_cycle, p_uart_cycle; + long long p_io_update_tcycle; + /*record CCCR,to get current core frequency */ + ARMword cccr; +}; +#if 0 +#define MAX_BANK 8 +#define MAX_STR 1024 + +typedef struct mem_bank +{ + ARMword (*read_byte) (ARMul_State* state, ARMword addr); + void (*write_byte) (ARMul_State* state, ARMword addr, ARMword data); + ARMword (*read_halfword) (ARMul_State* state, ARMword addr); + void (*write_halfword) (ARMul_State* state, ARMword addr, ARMword data); + ARMword (*read_word) (ARMul_State* state, ARMword addr); + void (*write_word) (ARMul_State* state, ARMword addr, ARMword data); + unsigned int addr, len; + char filename[MAX_STR]; + unsigned type; //chy 2003-09-21: maybe io,ram,rom +} mem_bank_t; +typedef struct +{ + int bank_num; + int current_num; /*current num of bank */ + mem_bank_t mem_banks[MAX_BANK]; +} mem_config_t; +#endif +#define VFP_REG_NUM 64 +#define bb_map std::unordered_map + +struct ARMul_State +{ + ARMword Emulate; /* to start and stop emulation */ + unsigned EndCondition; /* reason for stopping */ + unsigned ErrorCode; /* type of illegal instruction */ + + /* Order of the following register should not be modified */ + ARMword Reg[16]; /* the current register file */ + ARMword Cpsr; /* the current psr */ + ARMword Spsr_copy; + ARMword phys_pc; + ARMword Reg_usr[2]; + ARMword Reg_svc[2]; /* R13_SVC R14_SVC */ + ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */ + ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */ + ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */ + ARMword Reg_firq[7]; /* R8---R14 FIRQ */ + ARMword Spsr[7]; /* the exception psr's */ + ARMword Mode; /* the current mode */ + ARMword Bank; /* the current register bank */ + ARMword exclusive_tag; /* the address for which the local monitor is in exclusive access mode */ + ARMword exclusive_state; + ARMword exclusive_result; + ARMword CP15[VFP_BASE - CP15_BASE]; + ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */ + /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). + VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), + and only 32 singleword registers are accessible (S0-S31). */ + ARMword ExtReg[VFP_REG_NUM]; + /* ---- End of the ordered registers ---- */ + + ARMword RegBank[7][16]; /* all the registers */ + //chy:2003-08-19, used in arm xscale + /* 40 bit accumulator. We always keep this 64 bits wide, + and move only 40 bits out of it in an MRA insn. */ + ARMdword Accumulator; + + ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ + unsigned long long int icounter, debug_icounter, kernel_icounter; + unsigned int shifter_carry_out; + //ARMword translate_pc; + + /* add armv6 flags dyf:2010-08-09 */ + ARMword GEFlag, EFlag, AFlag, QFlag; + //chy:2003-08-19, used in arm v5e|xscale + ARMword SFlag; +#ifdef MODET + ARMword TFlag; /* Thumb state */ +#endif + ARMword instr, pc, temp; /* saved register state */ + ARMword loaded, decoded; /* saved pipeline state */ + //chy 2006-04-12 for ICE breakpoint + ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/ + unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ + unsigned long long NumInstrs; /* the number of instructions executed */ + unsigned NumInstrsToExecute; + + ARMword currentexaddr; + ARMword currentexval; + ARMword currentexvald; + ARMword servaddr; + + unsigned NextInstr; + unsigned VectorCatch; /* caught exception mask */ + unsigned CallDebug; /* set to call the debugger */ + unsigned CanWatch; /* set by memory interface if its willing to suffer the + overhead of checking for watchpoints on each memory + access */ + unsigned int StopHandle; + + char *CommandLine; /* Command Line from ARMsd */ + + ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ + ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ + ARMul_LDCs *LDC[16]; /* LDC instruction */ + ARMul_STCs *STC[16]; /* STC instruction */ + ARMul_MRCs *MRC[16]; /* MRC instruction */ + ARMul_MCRs *MCR[16]; /* MCR instruction */ + ARMul_MRRCs *MRRC[16]; /* MRRC instruction */ + ARMul_MCRRs *MCRR[16]; /* MCRR instruction */ + ARMul_CDPs *CDP[16]; /* CDP instruction */ + ARMul_CPReads *CPRead[16]; /* Read CP register */ + ARMul_CPWrites *CPWrite[16]; /* Write CP register */ + unsigned char *CPData[16]; /* Coprocessor data */ + unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ + + unsigned EventSet; /* the number of events in the queue */ + unsigned int Now; /* time to the nearest cycle */ + struct EventNode **EventPtr; /* the event list */ + + unsigned Debug; /* show instructions as they are executed */ + unsigned NresetSig; /* reset the processor */ + unsigned NfiqSig; + unsigned NirqSig; + + unsigned abortSig; + unsigned NtransSig; + unsigned bigendSig; + unsigned prog32Sig; + unsigned data32Sig; + unsigned syscallSig; + +/* 2004-05-09 chy +---------------------------------------------------------- +read ARM Architecture Reference Manual +2.6.5 Data Abort +There are three Abort Model in ARM arch. + +Early Abort Model: used in some ARMv3 and earlier implementations. In this +model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and +the base register was unchanged for all other instructions. (oldest) + +Base Restored Abort Model: If a Data Abort occurs in an instruction which +specifies base register writeback, the value in the base register is +unchanged. (strongarm, xscale) + +Base Updated Abort Model: If a Data Abort occurs in an instruction which +specifies base register writeback, the base register writeback still occurs. +(arm720T) + +read PART B +chap2 The System Control Coprocessor CP15 +2.4 Register1:control register +L(bit 6): in some ARMv3 and earlier implementations, the abort model of the +processor could be configured: +0=early Abort Model Selected(now obsolete) +1=Late Abort Model selceted(same as Base Updated Abort Model) + +on later processors, this bit reads as 1 and ignores writes. +------------------------------------------------------------- +So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) + if lateabtSig=0, then it means Base Restored Abort Model +*/ + unsigned lateabtSig; + + ARMword Vector; /* synthesize aborts in cycle modes */ + ARMword Aborted; /* sticky flag for aborts */ + ARMword Reseted; /* sticky flag for Reset */ + ARMword Inted, LastInted; /* sticky flags for interrupts */ + ARMword Base; /* extra hand for base writeback */ + ARMword AbortAddr; /* to keep track of Prefetch aborts */ + + const struct Dbg_HostosInterface *hostif; + + int verbose; /* non-zero means print various messages like the banner */ + + int mmu_inited; + //mem_state_t mem; + /*remove io_state to skyeye_mach_*.c files */ + //io_state_t io; + /* point to a interrupt pending register. now for skyeye-ne2k.c + * later should move somewhere. e.g machine_config_t*/ + + + //chy: 2003-08-11, for different arm core type + unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ + unsigned is_v5; /* Are we emulating a v5 architecture ? */ + unsigned is_v5e; /* Are we emulating a v5e architecture ? */ + unsigned is_v6; /* Are we emulating a v6 architecture ? */ + unsigned is_v7; /* Are we emulating a v7 architecture ? */ + unsigned is_XScale; /* Are we emulating an XScale architecture ? */ + unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ + unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ + //chy 2005-09-19 + unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */ + //chy: seems only used in xscale's CP14 + unsigned int LastTime; /* Value of last call to ARMul_Time() */ + ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */ + + + //added by ksh:for handle different machs io 2004-3-5 + ARMul_io mach_io; + + /*added by ksh,2004-11-26,some energy profiling*/ + ARMul_Energy energy; + + //teawater add for next_dis 2004.10.27----------------------- + int disassemble; + + + //teawater add for arm2x86 2005.02.15------------------------------------------- + u32 trap; + u32 tea_break_addr; + u32 tea_break_ok; + int tea_pc; + + //teawater add for arm2x86 2005.07.05------------------------------------------- + //arm_arm A2-18 + int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model + + //teawater change for return if running tb dirty 2005.07.09--------------------- + void *tb_now; + + + //teawater add for record reg value to ./reg.txt 2005.07.10--------------------- + FILE *tea_reg_fd; + + + /*added by ksh in 2005-10-1*/ + cpu_config_t *cpu; + //mem_config_t *mem_bank; + + /* added LPC remap function */ + int vector_remap_flag; + u32 vector_remap_addr; + u32 vector_remap_size; + + u32 step; + u32 cycle; + int stop_simulator; + conf_object_t *dyncom_cpu; +//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- +#ifdef DBCT_TEST_SPEED + uint64_t instr_count; +#endif //DBCT_TEST_SPEED +// FILE * state_log; +//diff log +//#if DIFF_STATE + FILE * state_log; +//#endif + /* monitored memory for exclusice access */ + ARMword exclusive_tag_array[128]; + /* 1 means exclusive access and 0 means open access */ + ARMword exclusive_access_state; + + memory_space_intf space; + u32 CurrInstr; + u32 last_pc; /* the last pc executed */ + u32 last_instr; /* the last inst executed */ + u32 WriteAddr[17]; + u32 WriteData[17]; + u32 WritePc[17]; + u32 CurrWrite; + + //memory map + KMemoryMap * m_MemoryMap; + KThread * m_currentThread; + + //ichfly fixes + char *inst_buf; + int inst_bufftop; + int inst_buffsize; + bb_map *CreamCache; +}; +#define DIFF_WRITE 0 + +typedef ARMul_State arm_core_t; +#define ResetPin NresetSig +#define FIQPin NfiqSig +#define IRQPin NirqSig +#define AbortPin abortSig +#define TransPin NtransSig +#define BigEndPin bigendSig +#define Prog32Pin prog32Sig +#define Data32Pin data32Sig +#define LateAbortPin lateabtSig + +/***************************************************************************\ +* Types of ARM we know about * +\***************************************************************************/ + +/* The bitflags */ +#define ARM_Fix26_Prop 0x01 +#define ARM_Nexec_Prop 0x02 +#define ARM_Debug_Prop 0x10 +#define ARM_Isync_Prop ARM_Debug_Prop +#define ARM_Lock_Prop 0x20 +#define ARM_v4_Prop 0x40 +#define ARM_v5_Prop 0x80 +#define ARM_v6_Prop 0xc0 + +#define ARM_v5e_Prop 0x100 +#define ARM_XScale_Prop 0x200 +#define ARM_ep9312_Prop 0x400 +#define ARM_iWMMXt_Prop 0x800 +#define ARM_PXA27X_Prop 0x1000 +#define ARM_v7_Prop 0x2000 + +/* ARM2 family */ +#define ARM2 (ARM_Fix26_Prop) +#define ARM2as ARM2 +#define ARM61 ARM2 +#define ARM3 ARM2 + +#ifdef ARM60 /* previous definition in armopts.h */ +#undef ARM60 +#endif + +/* ARM6 family */ +#define ARM6 (ARM_Lock_Prop) +#define ARM60 ARM6 +#define ARM600 ARM6 +#define ARM610 ARM6 +#define ARM620 ARM6 + + +/***************************************************************************\ +* Macros to extract instruction fields * +\***************************************************************************/ + +#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ +#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ +#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ + +/***************************************************************************\ +* The hardware vector addresses * +\***************************************************************************/ + +#define ARMResetV 0L +#define ARMUndefinedInstrV 4L +#define ARMSWIV 8L +#define ARMPrefetchAbortV 12L +#define ARMDataAbortV 16L +#define ARMAddrExceptnV 20L +#define ARMIRQV 24L +#define ARMFIQV 28L +#define ARMErrorV 32L /* This is an offset, not an address ! */ + +#define ARMul_ResetV ARMResetV +#define ARMul_UndefinedInstrV ARMUndefinedInstrV +#define ARMul_SWIV ARMSWIV +#define ARMul_PrefetchAbortV ARMPrefetchAbortV +#define ARMul_DataAbortV ARMDataAbortV +#define ARMul_AddrExceptnV ARMAddrExceptnV +#define ARMul_IRQV ARMIRQV +#define ARMul_FIQV ARMFIQV + +/***************************************************************************\ +* Mode and Bank Constants * +\***************************************************************************/ + +#define USER26MODE 0L +#define FIQ26MODE 1L +#define IRQ26MODE 2L +#define SVC26MODE 3L +#define USER32MODE 16L +#define FIQ32MODE 17L +#define IRQ32MODE 18L +#define SVC32MODE 19L +#define ABORT32MODE 23L +#define UNDEF32MODE 27L +//chy 2006-02-15 add system32 mode +#define SYSTEM32MODE 31L + +#define ARM32BITMODE (state->Mode > 3) +#define ARM26BITMODE (state->Mode <= 3) +#define ARMMODE (state->Mode) +#define ARMul_MODEBITS 0x1fL +#define ARMul_MODE32BIT ARM32BITMODE +#define ARMul_MODE26BIT ARM26BITMODE + +#define USERBANK 0 +#define FIQBANK 1 +#define IRQBANK 2 +#define SVCBANK 3 +#define ABORTBANK 4 +#define UNDEFBANK 5 +#define DUMMYBANK 6 +#define SYSTEMBANK USERBANK +#define BANK_CAN_ACCESS_SPSR(bank) \ + ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK) + + +/***************************************************************************\ +* Definitons of things in the emulator * +\***************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif +extern void ARMul_EmulateInit(); +extern void ARMul_Reset(ARMul_State* state); +#ifdef __cplusplus + } +#endif +extern ARMul_State *ARMul_NewState(ARMul_State* state); +extern ARMword ARMul_DoProg(ARMul_State* state); +extern ARMword ARMul_DoInstr(ARMul_State* state); +/***************************************************************************\ +* Definitons of things for event handling * +\***************************************************************************/ + +extern void ARMul_ScheduleEvent(ARMul_State* state, unsigned int delay, unsigned(*func) ()); +extern void ARMul_EnvokeEvent(ARMul_State* state); +extern unsigned int ARMul_Time(ARMul_State* state); + +/***************************************************************************\ +* Useful support routines * +\***************************************************************************/ + +extern ARMword ARMul_GetReg (ARMul_State* state, unsigned mode, unsigned reg); +extern void ARMul_SetReg (ARMul_State* state, unsigned mode, unsigned reg, ARMword value); +extern ARMword ARMul_GetPC(ARMul_State* state); +extern ARMword ARMul_GetNextPC(ARMul_State* state); +extern void ARMul_SetPC(ARMul_State* state, ARMword value); +extern ARMword ARMul_GetR15(ARMul_State* state); +extern void ARMul_SetR15(ARMul_State* state, ARMword value); + +extern ARMword ARMul_GetCPSR(ARMul_State* state); +extern void ARMul_SetCPSR(ARMul_State* state, ARMword value); +extern ARMword ARMul_GetSPSR(ARMul_State* state, ARMword mode); +extern void ARMul_SetSPSR(ARMul_State* state, ARMword mode, ARMword value); + +/***************************************************************************\ +* Definitons of things to handle aborts * +\***************************************************************************/ + +extern void ARMul_Abort(ARMul_State* state, ARMword address); +#ifdef MODET +#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */ +#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ + state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L)) +#else +#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ +#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ + state->AbortAddr = (address & ~3L) +#endif +#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ + state->Aborted = ARMul_DataAbortV ; +#define ARMul_CLEARABORT state->abortSig = LOW + +/***************************************************************************\ +* Definitons of things in the memory interface * +\***************************************************************************/ + +extern unsigned ARMul_MemoryInit(ARMul_State* state, unsigned int initmemsize); +extern void ARMul_MemoryExit(ARMul_State* state); + +extern ARMword ARMul_LoadInstrS(ARMul_State* state, ARMword address, ARMword isize); +extern ARMword ARMul_LoadInstrN(ARMul_State* state, ARMword address, ARMword isize); +#ifdef __cplusplus +extern "C" { +#endif +extern ARMword ARMul_ReLoadInstr(ARMul_State* state, ARMword address, ARMword isize); +#ifdef __cplusplus + } +#endif +extern ARMword ARMul_LoadWordS(ARMul_State* state, ARMword address); +extern ARMword ARMul_LoadWordN(ARMul_State* state, ARMword address); +extern ARMword ARMul_LoadHalfWord(ARMul_State* state, ARMword address); +extern ARMword ARMul_LoadByte(ARMul_State* state, ARMword address); + +extern void ARMul_StoreWordS(ARMul_State* state, ARMword address, ARMword data); +extern void ARMul_StoreWordN(ARMul_State* state, ARMword address, ARMword data); +extern void ARMul_StoreHalfWord(ARMul_State* state, ARMword address, ARMword data); +extern void ARMul_StoreByte(ARMul_State* state, ARMword address, ARMword data); + +extern ARMword ARMul_SwapWord(ARMul_State* state, ARMword address, ARMword data); +extern ARMword ARMul_SwapByte(ARMul_State* state, ARMword address, ARMword data); + +extern void ARMul_Icycles(ARMul_State* state, unsigned number, ARMword address); +extern void ARMul_Ccycles(ARMul_State* state, unsigned number, ARMword address); + +extern ARMword ARMul_ReadWord(ARMul_State* state, ARMword address); +extern ARMword ARMul_ReadByte(ARMul_State* state, ARMword address); +extern void ARMul_WriteWord(ARMul_State* state, ARMword address, ARMword data); +extern void ARMul_WriteByte(ARMul_State* state, ARMword address, ARMword data); +extern void ARMul_WriteDouble(ARMul_State* state, ARMword address, u64 data); + +extern ARMword ARMul_MemAccess(ARMul_State* state, ARMword, ARMword, + ARMword, ARMword, ARMword, ARMword, ARMword, + ARMword, ARMword, ARMword); + +/***************************************************************************\ +* Definitons of things in the co-processor interface * +\***************************************************************************/ + +#define ARMul_FIRST 0 +#define ARMul_TRANSFER 1 +#define ARMul_BUSY 2 +#define ARMul_DATA 3 +#define ARMul_INTERRUPT 4 +#define ARMul_DONE 0 +#define ARMul_CANT 1 +#define ARMul_INC 3 + +#define ARMul_CP13_R0_FIQ 0x1 +#define ARMul_CP13_R0_IRQ 0x2 +#define ARMul_CP13_R8_PMUS 0x1 + +#define ARMul_CP14_R0_ENABLE 0x0001 +#define ARMul_CP14_R0_CLKRST 0x0004 +#define ARMul_CP14_R0_CCD 0x0008 +#define ARMul_CP14_R0_INTEN0 0x0010 +#define ARMul_CP14_R0_INTEN1 0x0020 +#define ARMul_CP14_R0_INTEN2 0x0040 +#define ARMul_CP14_R0_FLAG0 0x0100 +#define ARMul_CP14_R0_FLAG1 0x0200 +#define ARMul_CP14_R0_FLAG2 0x0400 +#define ARMul_CP14_R10_MOE_IB 0x0004 +#define ARMul_CP14_R10_MOE_DB 0x0008 +#define ARMul_CP14_R10_MOE_BT 0x000c +#define ARMul_CP15_R1_ENDIAN 0x0080 +#define ARMul_CP15_R1_ALIGN 0x0002 +#define ARMul_CP15_R5_X 0x0400 +#define ARMul_CP15_R5_ST_ALIGN 0x0001 +#define ARMul_CP15_R5_IMPRE 0x0406 +#define ARMul_CP15_R5_MMU_EXCPT 0x0400 +#define ARMul_CP15_DBCON_M 0x0100 +#define ARMul_CP15_DBCON_E1 0x000c +#define ARMul_CP15_DBCON_E0 0x0003 + +extern unsigned ARMul_CoProInit(ARMul_State* state); +extern void ARMul_CoProExit(ARMul_State* state); +extern void ARMul_CoProAttach (ARMul_State* state, unsigned number, + ARMul_CPInits* init, ARMul_CPExits* exit, + ARMul_LDCs* ldc, ARMul_STCs* stc, + ARMul_MRCs* mrc, ARMul_MCRs* mcr, + ARMul_MRRCs* mrrc, ARMul_MCRRs* mcrr, + ARMul_CDPs* cdp, + ARMul_CPReads* read, ARMul_CPWrites* write); +extern void ARMul_CoProDetach(ARMul_State* state, unsigned number); + +/***************************************************************************\ +* Definitons of things in the host environment * +\***************************************************************************/ + +extern unsigned ARMul_OSInit(ARMul_State* state); +extern void ARMul_OSExit(ARMul_State* state); + +#ifdef __cplusplus + extern "C" { +#endif + +extern unsigned ARMul_OSHandleSWI(ARMul_State* state, ARMword number); +#ifdef __cplusplus +} +#endif + + +extern ARMword ARMul_OSLastErrorP(ARMul_State* state); + +extern ARMword ARMul_Debug(ARMul_State* state, ARMword pc, ARMword instr); +extern unsigned ARMul_OSException(ARMul_State* state, ARMword vector, ARMword pc); +extern int rdi_log; + +enum ConditionCode { + EQ = 0, + NE = 1, + CS = 2, + CC = 3, + MI = 4, + PL = 5, + VS = 6, + VC = 7, + HI = 8, + LS = 9, + GE = 10, + LT = 11, + GT = 12, + LE = 13, + AL = 14, + NV = 15, +}; + +#ifndef NFLAG +#define NFLAG state->NFlag +#endif //NFLAG + +#ifndef ZFLAG +#define ZFLAG state->ZFlag +#endif //ZFLAG + +#ifndef CFLAG +#define CFLAG state->CFlag +#endif //CFLAG + +#ifndef VFLAG +#define VFLAG state->VFlag +#endif //VFLAG + +#ifndef IFLAG +#define IFLAG (state->IFFlags >> 1) +#endif //IFLAG + +#ifndef FFLAG +#define FFLAG (state->IFFlags & 1) +#endif //FFLAG + +#ifndef IFFLAGS +#define IFFLAGS state->IFFlags +#endif //VFLAG + +#define FLAG_MASK 0xf0000000 +#define NBIT_SHIFT 31 +#define ZBIT_SHIFT 30 +#define CBIT_SHIFT 29 +#define VBIT_SHIFT 28 + +#define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\ + state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \ + state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \ + state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \ + state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \ + state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\ + state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\ + state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\ + state->temp,state->loaded,state->decoded);} + +#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\ +RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ +RF %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ +RI %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ +RS %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ +RA %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ +RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\ + state->RegBank[0][0],state->RegBank[0][1],state->RegBank[0][2],state->RegBank[0][3], \ + state->RegBank[0][4],state->RegBank[0][5],state->RegBank[0][6],state->RegBank[0][7], \ + state->RegBank[0][8],state->RegBank[0][9],state->RegBank[0][10],state->RegBank[0][11], \ + state->RegBank[0][12],state->RegBank[0][13],state->RegBank[0][14],state->RegBank[0][15], \ + state->RegBank[1][0],state->RegBank[1][1],state->RegBank[1][2],state->RegBank[1][3], \ + state->RegBank[1][4],state->RegBank[1][5],state->RegBank[1][6],state->RegBank[1][7], \ + state->RegBank[1][8],state->RegBank[1][9],state->RegBank[1][10],state->RegBank[1][11], \ + state->RegBank[1][12],state->RegBank[1][13],state->RegBank[1][14],state->RegBank[1][15], \ + state->RegBank[2][0],state->RegBank[2][1],state->RegBank[2][2],state->RegBank[2][3], \ + state->RegBank[2][4],state->RegBank[2][5],state->RegBank[2][6],state->RegBank[2][7], \ + state->RegBank[2][8],state->RegBank[2][9],state->RegBank[2][10],state->RegBank[2][11], \ + state->RegBank[2][12],state->RegBank[2][13],state->RegBank[2][14],state->RegBank[2][15], \ + state->RegBank[3][0],state->RegBank[3][1],state->RegBank[3][2],state->RegBank[3][3], \ + state->RegBank[3][4],state->RegBank[3][5],state->RegBank[3][6],state->RegBank[3][7], \ + state->RegBank[3][8],state->RegBank[3][9],state->RegBank[3][10],state->RegBank[3][11], \ + state->RegBank[3][12],state->RegBank[3][13],state->RegBank[3][14],state->RegBank[3][15], \ + state->RegBank[4][0],state->RegBank[4][1],state->RegBank[4][2],state->RegBank[4][3], \ + state->RegBank[4][4],state->RegBank[4][5],state->RegBank[4][6],state->RegBank[4][7], \ + state->RegBank[4][8],state->RegBank[4][9],state->RegBank[4][10],state->RegBank[4][11], \ + state->RegBank[4][12],state->RegBank[4][13],state->RegBank[4][14],state->RegBank[4][15], \ + state->RegBank[5][0],state->RegBank[5][1],state->RegBank[5][2],state->RegBank[5][3], \ + state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \ + state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \ + state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \ + );} + + +#define SA1110 0x6901b110 +#define SA1100 0x4401a100 +#define PXA250 0x69052100 +#define PXA270 0x69054110 +//#define PXA250 0x69052903 +// 0x69052903; //PXA250 B1 from intel 278522-001.pdf + +extern bool AddOverflow(ARMword, ARMword, ARMword); +extern bool SubOverflow(ARMword, ARMword, ARMword); + +extern void ARMul_UndefInstr(ARMul_State*, ARMword); +extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword); +extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword); +extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...); +extern void ARMul_SelectProcessor(ARMul_State*, unsigned); + +extern u32 AddWithCarry(u32, u32, u32, bool*, bool*); +extern bool ARMul_AddOverflowQ(ARMword, ARMword); + +extern u8 ARMul_SignedSaturatedAdd8(u8, u8); +extern u8 ARMul_SignedSaturatedSub8(u8, u8); +extern u16 ARMul_SignedSaturatedAdd16(u16, u16); +extern u16 ARMul_SignedSaturatedSub16(u16, u16); + +extern u8 ARMul_UnsignedSaturatedAdd8(u8, u8); +extern u16 ARMul_UnsignedSaturatedAdd16(u16, u16); +extern u8 ARMul_UnsignedSaturatedSub8(u8, u8); +extern u16 ARMul_UnsignedSaturatedSub16(u16, u16); +extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8); +extern u32 ARMul_SignedSatQ(s32, u8, bool*); +extern u32 ARMul_UnsignedSatQ(s32, u8, bool*); + +extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); +extern void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); + + + +#define DIFF_LOG 0 +#define SAVE_LOG 0 + +#endif /* _ARMDEFS_H_ */ diff --git a/source/arm/skyeye_common/armemu.h b/source/arm/skyeye_common/armemu.h new file mode 100644 index 0000000..2310e89 --- /dev/null +++ b/source/arm/skyeye_common/armemu.h @@ -0,0 +1,634 @@ +/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#ifndef __ARMEMU_H__ +#define __ARMEMU_H__ + + +#include "arm/skyeye_common/armdefs.h" +//#include "skyeye.h" + +//extern ARMword isize; + +/* Shift Opcodes. */ +#define LSL 0 +#define LSR 1 +#define ASR 2 +#define ROR 3 + +/* Macros to twiddle the status flags and mode. */ +#define NBIT ((unsigned)1L << 31) +#define ZBIT (1L << 30) +#define CBIT (1L << 29) +#define VBIT (1L << 28) +#define QBIT (1L << 27) +#define IBIT (1L << 7) +#define FBIT (1L << 6) +#define IFBITS (3L << 6) +#define R15IBIT (1L << 27) +#define R15FBIT (1L << 26) +#define R15IFBITS (3L << 26) + +#ifdef MODET /* Thumb support. */ +/* ??? This bit is actually in the low order bit of the PC in the hardware. + It isn't clear if the simulator needs to model that or not. */ +#define TBIT (1L << 5) +#define TFLAG state->TFlag +#define SETT state->TFlag = 1 +#define CLEART state->TFlag = 0 +#define ASSIGNT(res) state->TFlag = res +#define INSN_SIZE (TFLAG ? 2 : 4) +#else +#define INSN_SIZE 4 +#endif + +/*add armv6 CPSR feature*/ +#define EFLAG state->EFlag +#define SETE state->EFlag = 1 +#define CLEARE state->EFlag = 0 +#define ASSIGNE(res) state->NFlag = res + +#define AFLAG state->AFlag +#define SETA state->AFlag = 1 +#define CLEARA state->AFlag = 0 +#define ASSIGNA(res) state->NFlag = res + +#define QFLAG state->QFlag +#define SETQ state->QFlag = 1 +#define CLEARQ state->AFlag = 0 +#define ASSIGNQ(res) state->QFlag = res + +/* add end */ + +#define NFLAG state->NFlag +#define SETN state->NFlag = 1 +#define CLEARN state->NFlag = 0 +#define ASSIGNN(res) state->NFlag = res + +#define ZFLAG state->ZFlag +#define SETZ state->ZFlag = 1 +#define CLEARZ state->ZFlag = 0 +#define ASSIGNZ(res) state->ZFlag = res + +#define CFLAG state->CFlag +#define SETC state->CFlag = 1 +#define CLEARC state->CFlag = 0 +#define ASSIGNC(res) state->CFlag = res + +#define VFLAG state->VFlag +#define SETV state->VFlag = 1 +#define CLEARV state->VFlag = 0 +#define ASSIGNV(res) state->VFlag = res + +#define SFLAG state->SFlag +#define SETS state->SFlag = 1 +#define CLEARS state->SFlag = 0 +#define ASSIGNS(res) state->SFlag = res + +#define IFLAG (state->IFFlags >> 1) +#define FFLAG (state->IFFlags & 1) +#define IFFLAGS state->IFFlags +#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) +#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; + +#define PSR_FBITS (0xff000000L) +#define PSR_SBITS (0x00ff0000L) +#define PSR_XBITS (0x0000ff00L) +#define PSR_CBITS (0x000000ffL) + +#if defined MODE32 || defined MODET +#define CCBITS (0xf8000000L) +#else +#define CCBITS (0xf0000000L) +#endif + +#define INTBITS (0xc0L) + +#if defined MODET && defined MODE32 +#define PCBITS (0xffffffffL) +#else +#define PCBITS (0xfffffffcL) +#endif + +#define MODEBITS (0x1fL) +#define R15INTBITS (3L << 26) + +#if defined MODET && defined MODE32 +#define R15PCBITS (0x03ffffffL) +#else +#define R15PCBITS (0x03fffffcL) +#endif + +#define R15PCMODEBITS (0x03ffffffL) +#define R15MODEBITS (0x3L) + +#ifdef MODE32 +#define PCMASK PCBITS +#define PCWRAP(pc) (pc) +#else +#define PCMASK R15PCBITS +#define PCWRAP(pc) ((pc) & R15PCBITS) +#endif + +#define PC (state->Reg[15] & PCMASK) +#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) +#define R15INT (state->Reg[15] & R15INTBITS) +#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) +#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) +#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) +#define R15PC (state->Reg[15] & R15PCBITS) +#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) +#define R15MODE (state->Reg[15] & R15MODEBITS) + +#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (QFLAG << 27)) +#define EINT (IFFLAGS << 6) +#define ER15INT (IFFLAGS << 26) +#define EMODE (state->Mode) +#define EGEBITS (state->GEFlag & 0x000F0000) + +#ifdef MODET +#define CPSR (ECC | EGEBITS | (EFLAG << 9) | (AFLAG << 8) | EINT | (TFLAG << 5) | EMODE) +#else +#define CPSR (ECC | EINT | EMODE) +#endif + +#ifdef MODE32 +#define PATCHR15 +#else +#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC +#endif + +#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) +#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) +#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) +#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) +#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) + +#define SETR15PSR(s) \ + do \ + { \ + if (state->Mode == USER26MODE) \ + { \ + state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ + ASSIGNN ((state->Reg[15] & NBIT) != 0); \ + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ + ASSIGNC ((state->Reg[15] & CBIT) != 0); \ + ASSIGNV ((state->Reg[15] & VBIT) != 0); \ + } \ + else \ + { \ + state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ + ARMul_R15Altered (state); \ + } \ + } \ + while (0) + +#define SETABORT(i, m, d) \ + do \ + { \ + int SETABORT_mode = (m); \ + \ + ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ + ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ + | (i) | SETABORT_mode)); \ + state->Reg[14] = temp - (d); \ + } \ + while (0) + +#ifndef MODE32 +#define VECTORS 0x20 +#define LEGALADDR 0x03ffffff +#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) +#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) +#endif + +#define INTERNALABORT(address) \ + do \ + { \ + if (address < VECTORS) \ + state->Aborted = ARMul_DataAbortV; \ + else \ + state->Aborted = ARMul_AddrExceptnV; \ + } \ + while (0) + +#ifdef MODE32 +#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) +#else +#define TAKEABORT \ + do \ + { \ + if (state->Aborted == ARMul_AddrExceptnV) \ + ARMul_Abort (state, ARMul_AddrExceptnV); \ + else \ + ARMul_Abort (state, ARMul_DataAbortV); \ + } \ + while (0) +#endif + +#define CPTAKEABORT \ + do \ + { \ + if (!state->Aborted) \ + ARMul_Abort (state, ARMul_UndefinedInstrV); \ + else if (state->Aborted == ARMul_AddrExceptnV) \ + ARMul_Abort (state, ARMul_AddrExceptnV); \ + else \ + ARMul_Abort (state, ARMul_DataAbortV); \ + } \ + while (0); + + +/* Different ways to start the next instruction. */ +#define SEQ 0 +#define NONSEQ 1 +#define PCINCEDSEQ 2 +#define PCINCEDNONSEQ 3 +#define PRIMEPIPE 4 +#define RESUME 8 + +/************************************/ +/* shenoubang 2012-3-11 */ +/* for armv7 DBG DMB DSB instr*/ +/************************************/ +#define MBReqTypes_Writes 0 +#define MBReqTypes_All 1 + +#define NORMALCYCLE state->NextInstr = 0 +#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ +#define BUSUSEDINCPCS \ + do \ + { \ + if (! state->is_v4) \ + { \ + /* A standard PC inc and an S cycle. */ \ + state->Reg[15] += INSN_SIZE; \ + state->NextInstr = (state->NextInstr & 0xff) | 2; \ + } \ + } \ + while (0) + +#define BUSUSEDINCPCN \ + do \ + { \ + if (state->is_v4) \ + BUSUSEDN; \ + else \ + { \ + /* A standard PC inc and an N cycle. */ \ + state->Reg[15] += INSN_SIZE; \ + state->NextInstr |= 3; \ + } \ + } \ + while (0) + +#define INCPC \ + do \ + { \ + /* A standard PC inc. */ \ + state->Reg[15] += INSN_SIZE; \ + state->NextInstr |= 2; \ + } \ + while (0) + +#define FLUSHPIPE state->NextInstr |= PRIMEPIPE + +/* Cycle based emulation. */ + +#define OUTPUTCP(i,a,b) +#define NCYCLE +#define SCYCLE +#define ICYCLE +#define CCYCLE +#define NEXTCYCLE(c) + +/* Macros to extract parts of instructions. */ +#define DESTReg (BITS (12, 15)) +#define LHSReg (BITS (16, 19)) +#define RHSReg (BITS ( 0, 3)) + +#define DEST (state->Reg[DESTReg]) + +#ifdef MODE32 +#ifdef MODET +#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC) : (state->Reg[LHSReg])) +#define RHS ((RHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC) : (state->Reg[RHSReg])) +#else +#define LHS (state->Reg[LHSReg]) +#define RHS (state->Reg[RHSReg]) +#endif +#else +#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) +#define RHS ((RHSReg == 15) ? R15PC : (state->Reg[RHSReg])) +#endif + +#define MULDESTReg (BITS (16, 19)) +#define MULLHSReg (BITS ( 0, 3)) +#define MULRHSReg (BITS ( 8, 11)) +#define MULACCReg (BITS (12, 15)) + +#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) +#define DPSImmRHS temp = BITS(0,11) ; \ + rhs = ARMul_ImmedTable[temp] ; \ + if (temp > 255) /* There was a shift. */ \ + ASSIGNC (rhs >> 31) ; + +#ifdef MODE32 +#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ + : GetDPRegRHS (state, instr)) +#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ + : GetDPSRegRHS (state, instr)) +#else +#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetDPRegRHS (state, instr)) +#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetDPSRegRHS (state, instr)) +#endif + +#define LSBase state->Reg[LHSReg] +#define LSImmRHS (BITS(0,11)) + +#ifdef MODE32 +#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ + : GetLSRegRHS (state, instr)) +#else +#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetLSRegRHS (state, instr)) +#endif + +#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ + (ARMword) ARMul_BitList[BITS (8, 15)] ) +#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ + (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) + +#define SWAPSRC (state->Reg[RHSReg]) + +#define LSCOff (BITS (0, 7) << 2) +#define CPNum BITS (8, 11) + +/* Determine if access to coprocessor CP is permitted. + The XScale has a register in CP15 which controls access to CP0 - CP13. */ +//chy 2003-09-03, new CP_ACCESS_ALLOWED +/* +#define CP_ACCESS_ALLOWED(STATE, CP) \ + ( ((CP) >= 14) \ + || (! (STATE)->is_XScale) \ + || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) +*/ +#define CP_ACCESS_ALLOWED(STATE, CP) \ + ( ((CP) >= 14) ) \ + +/* Macro to rotate n right by b bits. */ +#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) + +/* Macros to store results of instructions. */ +#define WRITEDEST(d) \ + do \ + { \ + if (DESTReg == 15) \ + WriteR15 (state, d); \ + else \ + DEST = d; \ + } \ + while (0) + +#define WRITESDEST(d) \ + do \ + { \ + if (DESTReg == 15) \ + WriteSR15 (state, d); \ + else \ + { \ + DEST = d; \ + ARMul_NegZero (state, d); \ + } \ + } \ + while (0) + +#define WRITEDESTB(d) \ + do \ + { \ + if (DESTReg == 15){ \ + WriteR15Branch (state, d); \ + } \ + else{ \ + DEST = d; \ + } \ + } \ + while (0) + +#define BYTETOBUS(data) ((data & 0xff) | \ + ((data & 0xff) << 8) | \ + ((data & 0xff) << 16) | \ + ((data & 0xff) << 24)) + +#define BUSTOBYTE(address, data) \ + do \ + { \ + if (state->bigendSig) \ + temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ + else \ + temp = (data >> ((address & 3) << 3)) & 0xff; \ + } \ + while (0) + +#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) +#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) +#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) +#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) + +#define POSBRANCH ((instr & 0x7fffff) << 2) +#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) + + +/* Values for Emulate. */ +#define STOP 0 /* stop */ +#define CHANGEMODE 1 /* change mode */ +#define ONCE 2 /* execute just one interation */ +#define RUN 3 /* continuous execution */ + +/* Stuff that is shared across modes. */ +extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ +extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ +extern char ARMul_BitList[]; /* Number of bits in a byte table. */ + +#define EVENTLISTSIZE 1024L + +/* Thumb support. */ +typedef enum +{ + t_undefined, /* Undefined Thumb instruction. */ + t_decoded, /* Instruction decoded to ARM equivalent. */ + t_branch, /* Thumb branch (already processed). */ + t_uninitialized +} +tdstate; + +/********************************************************************************* + * Check all the possible undef or unpredict behavior, Some of them probably is + * out-of-updated with the newer ISA. + * -- Michael.Kang + ********************************************************************************/ +#define UNDEF_WARNING LOG("undefined or unpredicted behavior for arm instruction."); + +/* Macros to scrutinize instructions. */ +#define UNDEF_Test UNDEF_WARNING +//#define UNDEF_Test + +//#define UNDEF_Shift UNDEF_WARNING +#define UNDEF_Shift + +//#define UNDEF_MSRPC UNDEF_WARNING +#define UNDEF_MSRPC + +//#define UNDEF_MRSPC UNDEF_WARNING +#define UNDEF_MRSPC + +#define UNDEF_MULPCDest UNDEF_WARNING +//#define UNDEF_MULPCDest + +#define UNDEF_MULDestEQOp1 UNDEF_WARNING +//#define UNDEF_MULDestEQOp1 + +//#define UNDEF_LSRBPC UNDEF_WARNING +#define UNDEF_LSRBPC + +//#define UNDEF_LSRBaseEQOffWb UNDEF_WARNING +#define UNDEF_LSRBaseEQOffWb + +//#define UNDEF_LSRBaseEQDestWb UNDEF_WARNING +#define UNDEF_LSRBaseEQDestWb + +//#define UNDEF_LSRPCBaseWb UNDEF_WARNING +#define UNDEF_LSRPCBaseWb + +//#define UNDEF_LSRPCOffWb UNDEF_WARNING +#define UNDEF_LSRPCOffWb + +//#define UNDEF_LSMNoRegs UNDEF_WARNING +#define UNDEF_LSMNoRegs + +//#define UNDEF_LSMPCBase UNDEF_WARNING +#define UNDEF_LSMPCBase + +//#define UNDEF_LSMUserBankWb UNDEF_WARNING +#define UNDEF_LSMUserBankWb + +//#define UNDEF_LSMBaseInListWb UNDEF_WARNING +#define UNDEF_LSMBaseInListWb + +#define UNDEF_SWPPC UNDEF_WARNING +//#define UNDEF_SWPPC + +#define UNDEF_CoProHS UNDEF_WARNING +//#define UNDEF_CoProHS + +#define UNDEF_MCRPC UNDEF_WARNING +//#define UNDEF_MCRPC + +//#define UNDEF_LSCPCBaseWb UNDEF_WARNING +#define UNDEF_LSCPCBaseWb + +#define UNDEF_UndefNotBounced UNDEF_WARNING +//#define UNDEF_UndefNotBounced + +#define UNDEF_ShortInt UNDEF_WARNING +//#define UNDEF_ShortInt + +#define UNDEF_IllegalMode UNDEF_WARNING +//#define UNDEF_IllegalMode + +#define UNDEF_Prog32SigChange UNDEF_WARNING +//#define UNDEF_Prog32SigChange + +#define UNDEF_Data32SigChange UNDEF_WARNING +//#define UNDEF_Data32SigChange + +/* Prototypes for exported functions. */ +extern unsigned ARMul_NthReg (ARMword, unsigned); + +/* Prototypes for exported functions. */ +#ifdef __cplusplus + extern "C" { +#endif +extern ARMword ARMul_Emulate26 (ARMul_State *); +extern ARMword ARMul_Emulate32 (ARMul_State *); +#ifdef __cplusplus + } +#endif +extern unsigned IntPending (ARMul_State *); +extern void ARMul_CPSRAltered (ARMul_State *); +extern void ARMul_R15Altered (ARMul_State *); +extern ARMword ARMul_GetPC (ARMul_State *); +extern ARMword ARMul_GetNextPC (ARMul_State *); +extern ARMword ARMul_GetR15 (ARMul_State *); +extern ARMword ARMul_GetCPSR (ARMul_State *); +extern void ARMul_EnvokeEvent (ARMul_State *); +extern unsigned int ARMul_Time (ARMul_State *); +extern void ARMul_NegZero (ARMul_State *, ARMword); +extern void ARMul_SetPC (ARMul_State *, ARMword); +extern void ARMul_SetR15 (ARMul_State *, ARMword); +extern void ARMul_SetCPSR (ARMul_State *, ARMword); +extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); +extern void ARMul_Abort26 (ARMul_State *, ARMword); +extern void ARMul_Abort32 (ARMul_State *, ARMword); +extern ARMword ARMul_MRC (ARMul_State *, ARMword); +extern void ARMul_MRRC (ARMul_State *, ARMword, ARMword *, ARMword *); +extern void ARMul_CDP (ARMul_State *, ARMword); +extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); +extern void ARMul_STC (ARMul_State *, ARMword, ARMword); +extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); +extern void ARMul_MCRR (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); +extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); +extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); +extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); +extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); +extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); +extern void ARMul_ScheduleEvent (ARMul_State *, unsigned int, + unsigned (*)(ARMul_State *)); +/* Coprocessor support functions. */ +extern unsigned ARMul_CoProInit (ARMul_State *); +extern void ARMul_CoProExit (ARMul_State *); +extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, + ARMul_CPExits *, ARMul_LDCs *, ARMul_STCs *, + ARMul_MRCs *, ARMul_MCRs *, ARMul_MRRCs *, ARMul_MCRRs *, + ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); +extern void ARMul_CoProDetach (ARMul_State *, unsigned); +extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); + +extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); +extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); +extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); + + +#endif diff --git a/source/arm/skyeye_common/armmmu.h b/source/arm/skyeye_common/armmmu.h new file mode 100644 index 0000000..30858f9 --- /dev/null +++ b/source/arm/skyeye_common/armmmu.h @@ -0,0 +1,137 @@ +/* + armmmu.c - Memory Management Unit emulation. + ARMulator extensions for the ARM7100 family. + Copyright (C) 1999 Ben Williamson + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _ARMMMU_H_ +#define _ARMMMU_H_ + + +#define WORD_SHT 2 +#define WORD_SIZE (1<mmu.control) +#define MMU_Enabled (state->mmu.control & CONTROL_MMU) +#define MMU_Disabled (!(MMU_Enabled)) +#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT) + +#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE) +#define MMU_ICacheDisabled (!(MMU_ICacheDisabled)) + +#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE) +#define MMU_DCacheDisabled (!(MMU_DCacheEnabled)) + +#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE) +#define MMU_CacheDisabled (!(MMU_CacheEnabled)) + +#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER) +#define MMU_WBDisabled (!(MMU_WBEnabled)) + +/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/ +#define PID_VA_MAP_MASK 0xfe000000 +//#define mmu_pid_va_map(va) ({\ +// ARMword ret; \ +// if ((va) & PID_VA_MAP_MASK)\ +// ret = (va); \ +// else \ +// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\ +// ret;\ +//}) +#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK)) + +/* FS[3:0] in the fault status register: */ + +typedef enum fault_t +{ + NO_FAULT = 0x0, + ALIGNMENT_FAULT = 0x1, + + SECTION_TRANSLATION_FAULT = 0x5, + PAGE_TRANSLATION_FAULT = 0x7, + SECTION_DOMAIN_FAULT = 0x9, + PAGE_DOMAIN_FAULT = 0xB, + SECTION_PERMISSION_FAULT = 0xD, + SUBPAGE_PERMISSION_FAULT = 0xF, + + /* defined by skyeye */ + TLB_READ_MISS = 0x30, + TLB_WRITE_MISS = 0x40, + +} fault_t; + +#endif /* _ARMMMU_H_ */ diff --git a/source/arm/skyeye_common/armos.h b/source/arm/skyeye_common/armos.h new file mode 100644 index 0000000..ffdadcd --- /dev/null +++ b/source/arm/skyeye_common/armos.h @@ -0,0 +1,131 @@ +/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#if FAST_MEMORY +/* in user mode, mmap_base will be on initial brk, + set at the first mmap request */ +#define mmap_base -1 +#else +#define mmap_base 0x50000000 +#endif +static long mmap_next_base = mmap_base; + +//static mmap_area_t* new_mmap_area(int sim_addr, int len); +static char mmap_mem_write(short size, int addr, uint32_t value); +static char mmap_mem_read(short size, int addr, uint32_t * value); + +/***************************************************************************\ +* SWI numbers * +\***************************************************************************/ + +#define SWI_Syscall 0x0 +#define SWI_Exit 0x1 +#define SWI_Read 0x3 +#define SWI_Write 0x4 +#define SWI_Open 0x5 +#define SWI_Close 0x6 +#define SWI_Seek 0x13 +#define SWI_Rename 0x26 +#define SWI_Break 0x11 + +#define SWI_Times 0x2b +#define SWI_Brk 0x2d + +#define SWI_Mmap 0x5a +#define SWI_Munmap 0x5b +#define SWI_Mmap2 0xc0 + +#define SWI_GetUID32 0xc7 +#define SWI_GetGID32 0xc8 +#define SWI_GetEUID32 0xc9 +#define SWI_GetEGID32 0xca + +#define SWI_ExitGroup 0xf8 + +#if 0 +#define SWI_Time 0xd +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Flen 0x6c +#endif + +#define SWI_Uname 0x7a +#define SWI_Fcntl 0xdd +#define SWI_Fstat64 0xc5 +#define SWI_Gettimeofday 0x4e +#define SWI_Set_tls 0xf0005 + +#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */ + +/***************************************************************************\ +* SWI structures * +\***************************************************************************/ + +/* Arm binaries (for now) only support 32 bit, and expect to receive + 32-bit compliant structure in return of a systen call. Because + we use host system calls to emulate system calls, the returned + structure can be 32-bit compliant or 64-bit compliant, depending + on the OS running skyeye. Therefore, we need a fixed size structure + adapted to arm.*/ + +/* Borrowed from qemu */ +struct target_stat64 { + unsigned short st_dev; + unsigned char __pad0[10]; + uint32_t __st_ino; + unsigned int st_mode; + unsigned int st_nlink; + uint32_t st_uid; + uint32_t st_gid; + unsigned short st_rdev; + unsigned char __pad3[10]; + unsigned char __pad31[4]; + long long st_size; + uint32_t st_blksize; + unsigned char __pad32[4]; + uint32_t st_blocks; + uint32_t __pad4; + uint32_t st32_atime; + uint32_t __pad5; + uint32_t st32_mtime; + uint32_t __pad6; + uint32_t st32_ctime; + uint32_t __pad7; + unsigned long long st_ino; +};// __attribute__((packed)); + +struct target_tms32 { + uint32_t tms_utime; + uint32_t tms_stime; + uint32_t tms_cutime; + uint32_t tms_cstime; +}; + +struct target_timeval32 { + uint32_t tv_sec; /* seconds */ + uint32_t tv_usec; /* microseconds */ +}; + +struct target_timezone32 { + int32_t tz_minuteswest; /* minutes west of Greenwich */ + int32_t tz_dsttime; /* type of DST correction */ +}; + diff --git a/source/arm/skyeye_common/skyeye_defs.h b/source/arm/skyeye_common/skyeye_defs.h new file mode 100644 index 0000000..712f0ef --- /dev/null +++ b/source/arm/skyeye_common/skyeye_defs.h @@ -0,0 +1,113 @@ +#ifndef CORE_ARM_SKYEYE_DEFS_H_ +#define CORE_ARM_SKYEYE_DEFS_H_ + +#include "Common.h" + +#define MODE32 +#define MODET + +typedef struct +{ + const char *cpu_arch_name; /*cpu architecture version name.e.g. armv4t */ + const char *cpu_name; /*cpu name. e.g. arm7tdmi or arm720t */ + u32 cpu_val; /*CPU value; also call MMU ID or processor id;see + ARM Architecture Reference Manual B2-6 */ + u32 cpu_mask; /*cpu_val's mask. */ + u32 cachetype; /*this cpu has what kind of cache */ +} cpu_config_t; + +typedef struct conf_object_s{ + char* objname; + void* obj; + char* class_name; +}conf_object_t; + +typedef enum{ + /* No exception */ + No_exp = 0, + /* Memory allocation exception */ + Malloc_exp, + /* File open exception */ + File_open_exp, + /* DLL open exception */ + Dll_open_exp, + /* Invalid argument exception */ + Invarg_exp, + /* Invalid module exception */ + Invmod_exp, + /* wrong format exception for config file parsing */ + Conf_format_exp, + /* some reference excess the predefiend range. Such as the index out of array range */ + Excess_range_exp, + /* Can not find the desirable result */ + Not_found_exp, + + /* Unknown exception */ + Unknown_exp +}exception_t; + +typedef enum { + Align = 0, + UnAlign +}align_t; + +typedef enum { + Little_endian = 0, + Big_endian +}endian_t; +//typedef int exception_t; + +typedef enum{ + Phys_addr = 0, + Virt_addr +}addr_type_t; + +typedef exception_t(*read_byte_t)(conf_object_t* target, u32 addr, void *buf, size_t count); +typedef exception_t(*write_byte_t)(conf_object_t* target, u32 addr, const void *buf, size_t count); + +typedef struct memory_space{ + conf_object_t* conf_obj; + read_byte_t read; + write_byte_t write; +}memory_space_intf; + + +/* + * a running instance for a specific archteciture. + */ +typedef struct generic_arch_s +{ + char* arch_name; + void (*init) (void); + void (*reset) (void); + void (*step_once) (void); + void (*set_pc)(u32 addr); + u32 (*get_pc)(void); + u32 (*get_step)(void); + //chy 2004-04-15 + //int (*ICE_write_byte) (u32 addr, uint8_t v); + //int (*ICE_read_byte)(u32 addr, uint8_t *pv); + u32 (*get_regval_by_id)(int id); + u32 (*get_regnum)(void); + char* (*get_regname_by_id)(int id); + exception_t (*set_regval_by_id)(int id, u32 value); + /* + * read a data by virtual address. + */ + exception_t (*mmu_read)(short size, u32 addr, u32 * value); + /* + * write a data by a virtual address. + */ + exception_t (*mmu_write)(short size, u32 addr, u32 value); + /** + * get a signal from external + */ + //exception_t (*signal)(interrupt_signal_t* signal); + + endian_t endianess; + align_t alignment; +} generic_arch_t; + +typedef u32 addr_t; + +#endif diff --git a/source/arm/skyeye_common/skyeye_types.h b/source/arm/skyeye_common/skyeye_types.h new file mode 100644 index 0000000..fc7d8d9 --- /dev/null +++ b/source/arm/skyeye_common/skyeye_types.h @@ -0,0 +1,31 @@ +/* + skyeye_types.h - some data types definition for skyeye debugger + Copyright (C) 2003 Skyeye Develop Group + for help please send mail to + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +*/ +/* + * 12/16/2006 Michael.Kang + */ + +#pragma once + +#include + +typedef uint32_t address_t; +typedef uint32_t physical_address_t; +typedef uint32_t generic_address_t; diff --git a/source/arm/skyeye_common/vfp/asm_vfp.h b/source/arm/skyeye_common/vfp/asm_vfp.h new file mode 100644 index 0000000..ccb7cf4 --- /dev/null +++ b/source/arm/skyeye_common/vfp/asm_vfp.h @@ -0,0 +1,83 @@ +/* + * arch/arm/include/asm/vfp.h + * + * VFP register definitions. + * First, the standard VFP set. + */ + +#pragma once + +// FPSID Information +// Note that these are used as values and not as flags. +enum : u32 { + VFP_FPSID_IMPLMEN = 0, // Implementation code. Should be the same as cp15 0 c0 0 + VFP_FPSID_SW = 0, // Software emulation bit value + VFP_FPSID_SUBARCH = 0x2, // Subarchitecture version number + VFP_FPSID_PARTNUM = 0x1, // Part number + VFP_FPSID_VARIANT = 0x1, // Variant number + VFP_FPSID_REVISION = 0x1 // Revision number +}; + +// FPEXC bits +enum : u32 { + FPEXC_EX = (1U << 31U), + FPEXC_EN = (1 << 30), + FPEXC_DEX = (1 << 29), + FPEXC_FP2V = (1 << 28), + FPEXC_VV = (1 << 27), + FPEXC_TFV = (1 << 26), + FPEXC_LENGTH_BIT = (8), + FPEXC_LENGTH_MASK = (7 << FPEXC_LENGTH_BIT), + FPEXC_IDF = (1 << 7), + FPEXC_IXF = (1 << 4), + FPEXC_UFF = (1 << 3), + FPEXC_OFF = (1 << 2), + FPEXC_DZF = (1 << 1), + FPEXC_IOF = (1 << 0), + FPEXC_TRAP_MASK = (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) +}; + +// FPSCR Flags +enum : u32 { + FPSCR_NFLAG = (1U << 31U), // Negative condition flag + FPSCR_ZFLAG = (1 << 30), // Zero condition flag + FPSCR_CFLAG = (1 << 29), // Carry condition flag + FPSCR_VFLAG = (1 << 28), // Overflow condition flag + + FPSCR_QC = (1 << 27), // Cumulative saturation bit + FPSCR_AHP = (1 << 26), // Alternative half-precision control bit + FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit + FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit + FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask + FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask + FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask + + FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable. + FPSCR_IXE = (1 << 12), // Inexact exception trap enable + FPSCR_UFE = (1 << 11), // Undeflow exception trap enable + FPSCR_OFE = (1 << 10), // Overflow exception trap enable + FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable + FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable + + FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit + FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit + FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit + FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit + FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit + FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit +}; + +// FPSCR bit offsets +enum : u32 { + FPSCR_RMODE_BIT = 22, + FPSCR_STRIDE_BIT = 20, + FPSCR_LENGTH_BIT = 16, +}; + +// FPSCR rounding modes +enum : u32 { + FPSCR_ROUND_NEAREST = (0 << 22), + FPSCR_ROUND_PLUSINF = (1 << 22), + FPSCR_ROUND_MINUSINF = (2 << 22), + FPSCR_ROUND_TOZERO = (3 << 22) +}; diff --git a/source/arm/skyeye_common/vfp/vfp.cpp b/source/arm/skyeye_common/vfp/vfp.cpp new file mode 100644 index 0000000..4f15c9d --- /dev/null +++ b/source/arm/skyeye_common/vfp/vfp.cpp @@ -0,0 +1,780 @@ +/* + armvfp.c - ARM VFPv3 emulation unit + Copyright (C) 2003 Skyeye Develop Group + for help please send mail to + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* Note: this file handles interface with arm core and vfp registers */ + +#include "Kernel.h" + +#include "arm/skyeye_common/armdefs.h" +#include "arm/skyeye_common/vfp/asm_vfp.h" +#include "arm/skyeye_common/vfp/vfp.h" + +#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) +#define BIT(s, n) ((s >> (n)) & 1) + +unsigned VFPInit(ARMul_State* state) +{ + state->VFP[VFP_OFFSET(VFP_FPSID)] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 | + VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION; + state->VFP[VFP_OFFSET(VFP_FPEXC)] = 0; + state->VFP[VFP_OFFSET(VFP_FPSCR)] = 0; + + return 0; +} + +unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value) +{ + /* MRC ,,,,{,} */ + int CoProc = BITS(instr, 8, 11); /* 10 or 11 */ + int OPC_1 = BITS(instr, 21, 23); + int Rt = BITS(instr, 12, 15); + int CRn = BITS(instr, 16, 19); + int CRm = BITS(instr, 0, 3); + int OPC_2 = BITS(instr, 5, 7); + + /* TODO check access permission */ + + /* CRn/opc1 CRm/opc2 */ + + if (CoProc == 10 || CoProc == 11) + { + if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0) + { + /* VMOV r to s */ + /* Transfering Rt is not mandatory, as the value of interest is pointed by value */ + VMOVBRS(state, BIT(instr, 20), Rt, BIT(instr, 7)|CRn<<1, value); + return ARMul_DONE; + } + + if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0) + { + VMRS(state, CRn, Rt, value); + return ARMul_DONE; + } + } + LOG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", + instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); + + return ARMul_CANT; +} + +unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value) +{ + /* MCR ,,,,{,} */ + int CoProc = BITS(instr, 8, 11); /* 10 or 11 */ + int OPC_1 = BITS(instr, 21, 23); + int Rt = BITS(instr, 12, 15); + int CRn = BITS(instr, 16, 19); + int CRm = BITS(instr, 0, 3); + int OPC_2 = BITS(instr, 5, 7); + + /* TODO check access permission */ + + /* CRn/opc1 CRm/opc2 */ + if (CoProc == 10 || CoProc == 11) + { + if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0) + { + /* VMOV s to r */ + /* Transfering Rt is not mandatory, as the value of interest is pointed by value */ + VMOVBRS(state, BIT(instr, 20), Rt, BIT(instr, 7)|CRn<<1, &value); + return ARMul_DONE; + } + + if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0) + { + VMSR(state, CRn, Rt); + return ARMul_DONE; + } + + if ((OPC_1 & 0x4) == 0 && CoProc == 11 && CRm == 0) + { + VFP_DEBUG_UNIMPLEMENTED(VMOVBRC); + return ARMul_DONE; + } + + if (CoProc == 11 && CRm == 0) + { + VFP_DEBUG_UNIMPLEMENTED(VMOVBCR); + return ARMul_DONE; + } + } + LOG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", + instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); + + return ARMul_CANT; +} + +unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32* value2) +{ + /* MCRR ,,,, */ + int CoProc = BITS(instr, 8, 11); /* 10 or 11 */ + int OPC_1 = BITS(instr, 4, 7); + int Rt = BITS(instr, 12, 15); + int Rt2 = BITS(instr, 16, 19); + int CRm = BITS(instr, 0, 3); + + if (CoProc == 10 || CoProc == 11) + { + if (CoProc == 10 && (OPC_1 & 0xD) == 1) + { + VMOVBRRSS(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, value1, value2); + return ARMul_DONE; + } + + if (CoProc == 11 && (OPC_1 & 0xD) == 1) + { + /* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */ + VMOVBRRD(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, value1, value2); + return ARMul_DONE; + } + } + LOG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", + instr, CoProc, OPC_1, Rt, Rt2, CRm); + + return ARMul_CANT; +} + +unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 value2) +{ + /* MCRR ,,,, */ + int CoProc = BITS(instr, 8, 11); /* 10 or 11 */ + int OPC_1 = BITS(instr, 4, 7); + int Rt = BITS(instr, 12, 15); + int Rt2 = BITS(instr, 16, 19); + int CRm = BITS(instr, 0, 3); + + /* TODO check access permission */ + + /* CRn/opc1 CRm/opc2 */ + + if (CoProc == 11 || CoProc == 10) + { + if (CoProc == 10 && (OPC_1 & 0xD) == 1) + { + VMOVBRRSS(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, &value1, &value2); + return ARMul_DONE; + } + + if (CoProc == 11 && (OPC_1 & 0xD) == 1) + { + /* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */ + VMOVBRRD(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, &value1, &value2); + return ARMul_DONE; + } + } + LOG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", + instr, CoProc, OPC_1, Rt, Rt2, CRm); + + return ARMul_CANT; +} + +unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value) +{ + /* STC{L} ,,[],